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| instruction set manual version 1.2, 12.97 ins t ruc t ion set manual for the c 1 6x family of siemens 1 6-bit cmos single-chip microcontrollers h t tp://www .siemens.de/ semiconductor/
version 1.2, 12.97 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support de- vice or system, or to affect its safety or ef- fectiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. c166 family microcontroller instruction set manual revision history: version 1.2, 12.97 previous releases: version 1.1, 09.95 03.94 page subjects 8 bfld* code size corrected 35 addcb: spelling corrected 38 ashr: "operation" corrected 43, 44 bfld*: note improved, format corrected 51 calli: "operation" corrected 67 einit: syntax corrected 75 jbc: condition flags corrected 77 jmpi: "operation" corrected 81 jnbs: condition flags corrected 86, 87 mul(u): flag n corrected 95 prior: "operation" corrected 104 scxt: data type added 108 srvwdt: syntax corrected we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@hl.siemens.de c166 family instruction set table of contents table of contents page semiconductor group 4 version 1.2, 12.97 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 short instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 instruction opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 instruction description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7 instruction state times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 30mar98@15:00h semiconductor group 5 version 1.2, 12.97 c166 family instruction set introduction 1 introduction the siemens family of 16-bit microcontrollers offers devices that provide various levels of peripheral performance and programmability. this allows to equip each specific application with the microcontroller that fits best to the required functionality and performance. still the siemens family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design. two major characteristics enable this upgrade path to save and reuse almost all of the engineering efforts that have been made for previous designs: ? all family members are based on the same basic architecture ? all family members execute the same instructions (except for upgrades for new members) the fact that all members execute the same instructions (almost) saves knowhow with respect to the understanding of the controller itself and also with respect to the used tools (assembler, disassembler, compiler, etc.). this instruction set manual provides an easy and direct access to the instructions of the siemens 16-bit microcontrollers by listing them according to different criteria, and also unloads the technical manuals for the different devices from redundant information. this manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses. there is also information provided to calculate the execution time for specific instructions depending on the used address locations and also specific exceptions to the standard rules. description levels in the following sections the instructions are compiled according to different criteria in order to provide different levels of precision: ? cross reference tables summarize all instructions in condensed tables ? the instruction set summary groups the individual instructions into functional groups ? the opcode table references the instructions by their hexadecimal opcode ? the instruction description describes each instruction in full detail all instructions listed in this manual are executed by the following devices (new derivatives will be added to this list): c161v, c161k, c161o, c161ri, c161si, c161ci, c163, c163f, c164ci, c165, c167, c167cr, c167sr, c167s, c167cs. a few instructions (atomic and extended instructions) have been added for these devices and are not recognized by the following devices: sab 80c166, sab 80c166w, sab 83c166, sab 83c166w, sab 88c166, sab 88c166w. these differences are noted for each instruction, where applicable. 30mar98@15:00h semiconductor group 6 version 1.2, 12.97 c166 family instruction set short instruction summary 2 short instruction summary the following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. two ordering schemes are included: the first table (two pages) is a compressed cross-reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic. the second table lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the selected addressing mode. this reference helps to optimize instruction sequences in terms of code size and/ or execution time. ?0x1x2x3x4x5x6x7x x0 add addc sub subc cmp xor and or x1 addb addcb subb subcb cmpb xorb andb orb x2 add addc sub subc cmp xor and or x3 addb addcb subb subcb cmpb xorb andb orb x4 add addc sub subc - xor and or x5 addb addcb subb subcb - xorb andb orb x6 add addc sub subc cmp xor and or x7 addb addcb subb subcb cmpb xorb andb orb x8 add addc sub subc cmp xor and or x9 addb addcb subb subcb cmpb xorb andb orb xa bfldl bfldh bcmp bmovn bmov bor band bxor xb mul mulu prior - div divu divl divlu xc rol rol ror ror shl shl shr shr xd jmpr jmpr jmpr jmpr jmpr jmpr jmpr jmpr xe bclr bclr bclr bclr bclr bclr bclr bclr xf bset bset bset bset bset bset bset bset 30mar98@15:00h semiconductor group 7 version 1.2, 12.97 c166 family instruction set short instruction summary note: both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailled lists in the following sections of this manual. note: the atomic and extended instructions are not available in the sab 8xc166(w) devices. they are marked in the cross-reference table. 8x 9x ax bx cx dx ex fx x0 cmpi1 cmpi2 cmpd1 cmpd2 movbz movbs mov mov x1 neg cpl negb cplb - at/extr movb movb x2 cmpi1 cmpi2 cmpd1 cmpd2 movbz movbs pcall mov x3 -------movb x4 mov mov movb movb mov mov movb movb x5 - - diswdt einit movbz movbs - - x6 cmpi1 cmpi2 cmpd1 cmpd2 scxt scxt mov mov x7 idle pwrdn srvwdt srst - extp/s/r movb movb x8 mov mov mov mov mov mov mov - x9 movb movb movb movb movb movb movb - xa jb jnb jbc jnbs calla calls jmpa jmps xb - trap calli callr ret rets retp reti xc - jmpi ashr ashr nop extp/s/r push pop xd jmpr jmpr jmpr jmpr jmpr jmpr jmpr jmpr xe bclr bclr bclr bclr bclr bclr bclr bclr xf bset bset bset bset bset bset bset bset 30mar98@15:00h semiconductor group 8 version 1.2, 12.97 c166 family instruction set short instruction summary 1) byte oriented instructions (suffix b) use rb instead of rw (not with [rwn]!). 2) byte oriented instructions (suffix b) use #data8 instead of #data16. 3) the atomic and extended instructions are not available in the sab 8xc166(w) devices. mnemonic addressing modesbytes mnemonic addressing modesbytes add[b] addc[b] and[b] or[b] sub[b] subc[b] xor[b] rwn rwm 1) rwn [rwi] 1) rwn [rwi+] 1) rwn #data3 1) reg #data16 2) reg mem mem reg 2 2 2 2 4 4 4 cpl[b] neg[b] rwn 1) 2 div divl divlu divu rwn 2 mul mulu rwn rwm 2 ashr rol / ror shl / shr rwn rwm rwn #data4 2 2 cmpd1/2 cmpi1/2 rwn #data4 rwn #data16 rwn mem 2 4 4 band bcmp bmov bmovn bor / bxor bitaddrz.z bitaddrq.q 4 cmp[b] rwn rwm 1) rwn [rwi] 1) rwn [rwi+] 1) rwn #data3 1) reg #data16 2) reg mem 2 2 2 2 4 4 bclr bset bitaddrq.q 2 calla jmpa cc caddr 4 bfldh bfldl bitoffq #mask8 #data8 4 calli jmpi cc [rwn] 2 mov[b] rwn rwm 1) rwn #data4 1) rwn [rwm] 1) rwn [rwm+] 1) [rwm] rwn 1) [-rwm] rwn 1) [rwn] [rwm] [rwn+] [rwm] [rwn] [rwm+] reg #data16 2) rwn [rwm+#d16] 1) [rwm+#d16] rwn 1) [rwn] mem mem [rwn] reg mem mem reg 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 calls jmps seg caddr 4 callr rel 2 jmpr cc rel 2 jb jbc jnb jnbs bitaddrq.q rel 4 pcall reg caddr 4 pop push retp reg 2 scxt reg #data16 reg mem 4 4 prior rwn rwm 2 movbs movbz rwn rbm reg mem mem reg 2 4 4 trap #trap7 2 atomic extr #irang2 3) 2 exts extsr rwm #irang2 3) #seg #irang2 2 4 extp extpr rwm #irang2 3) #pag #irang2 2 4 nop ret reti rets - 2 srst/idle pwrdn srvwdt diswdt einit -4 30mar98@15:00h semiconductor group 9 version 1.2, 12.97 c166 family instruction set instruction set summary 3 instruction set summary this chapter summarizes the instructions by listing them according to their functional class. this allows to identify the right instruction(s) for a specific required function. the following notes apply to this summary: data addressing modes rw: C word gpr (r0, r1, , r15) rb: C byte gpr (rl0, rh0, , rl7, rh7) reg: C sfr or gpr (in case of a byte operation on an sfr, only the low byte can be accessed via reg) mem: C direct word or byte memory location []: C indirect word or byte memory location (any word gpr can be used as indirect address pointer, except for the arithmetic, logical and compare instructions, where only r0 to r3 are allowed) bitaddr: C direct bit in the bit-addressable memory area bitoff: C direct word in the bit-addressable memory area #data: C immediate constant (the number of significant bits which can be specified by the user is represented by the respective appendix x) #mask8: C immediate 8-bit mask used for bit-field modifications multiply and divide operations the mdl and mdh registers are implicit source and/or destination operands of the multiply and divide instructions. branch target addressing modes caddr: C direct 16-bit jump target address (updates the instruction pointer) seg: C direct 2-bit segment address (updates the code segment pointer) rel: C signed 8-bit jump target word offset address relative to the instruction pointer of the following instruction #trap7: C immediate 7-bit trap or interrupt number. 30mar98@15:00h semiconductor group 10 version 1.2, 12.97 c166 family instruction set instruction set summary extension operations the ext* instructions override the standard dpp addressing scheme: #pag10: C immediate 10-bit page address. #seg8: C immediate 8-bit segment address. note: the extended instructions are not available in the sab 8xc166(w) devices. branch condition codes cc: symbolically specifiable condition codes cc_uc C unconditional cc_z C zero cc_nz C not zero cc_v C overflow cc_nv C no overflow cc_n C negative cc_nn C not negative cc_c C carry cc_nc C no carry cc_eq C equal cc_ne C not equal cc_ult C unsigned less than cc_ule C unsigned less than or equal cc_uge C unsigned greater than or equal cc_ugt C unsigned greater than cc_sle C signed less than or equal cc_sge C signed greater than or equal cc_sgt C signed greater than cc_net C not equal and not end-of-table 30mar98@15:00h semiconductor group 11 version 1.2, 12.97 c166 family instruction set instruction set summary instruction set summary mnemonic description bytes arithmetic operations add rw, rw add direct word gpr to direct gpr 2 add rw, [rw] add indirect word memory to direct gpr 2 add rw, [rw +] add indirect word memory to direct gpr and post- increment source pointer by 2 2 add rw, #data3 add immediate word data to direct gpr 2 add reg, #data16 add immediate word data to direct register 4 add reg, mem add direct word memory to direct register 4 add mem, reg add direct word register to direct memory 4 addb rb, rb add direct byte gpr to direct gpr 2 addb rb, [rw] add indirect byte memory to direct gpr 2 addb rb, [rw +] add indirect byte memory to direct gpr and post-increment source pointer by 1 2 addb rb, #data3 add immediate byte data to direct gpr 2 addb reg, #data8 add immediate byte data to direct register 4 addb reg, mem add direct byte memory to direct register 4 addb mem, reg add direct byte register to direct memory 4 addc rw, rw add direct word gpr to direct gpr with carry 2 addc rw, [rw] add indirect word memory to direct gpr with carry 2 addc rw, [rw +] add indirect word memory to direct gpr with carry and post-increment source pointer by 2 2 addc rw, #data3 add immediate word data to direct gpr with carry 2 addc reg, #data16 add immediate word data to direct register with carry 4 addc reg, mem add direct word memory to direct register with carry 4 addc mem, reg add direct word register to direct memory with carry 4 addcb rb, rb add direct byte gpr to direct gpr with carry 2 addcb rb, [rw] add indirect byte memory to direct gpr with carry 2 addcb rb, [rw +] add indirect byte memory to direct gpr with carry and post-increment source pointer by 1 2 addcb rb, #data3 add immediate byte data to direct gpr with carry 2 addcb reg, #data8 add immediate byte data to direct register with carry 4 addcb reg, mem add direct byte memory to direct register with carry 4 30mar98@15:00h semiconductor group 12 version 1.2, 12.97 c166 family instruction set instruction set summary arithmetic operations (contd) addcb mem, reg add direct byte register to direct memory with carry 4 sub rw, rw subtract direct word gpr from direct gpr 2 sub rw, [rw] subtract indirect word memory from direct gpr 2 sub rw, [rw +] subtract indirect word memory from direct gpr and post-increment source pointer by 2 2 sub rw, #data3 subtract immediate word data from direct gpr 2 sub reg, #data16 subtract immediate word data from direct register 4 sub reg, mem subtract direct word memory from direct register 4 sub mem, reg subtract direct word register from direct memory 4 subb rb, rb subtract direct byte gpr from direct gpr 2 subb rb, [rw] subtract indirect byte memory from direct gpr 2 subb rb, [rw +] subtract indirect byte memory from direct gpr and post-increment source pointer by 1 2 subb rb, #data3 subtract immediate byte data from direct gpr 2 subb reg, #data8 subtract immediate byte data from direct register 4 subb reg, mem subtract direct byte memory from direct register 4 subb mem, reg subtract direct byte register from direct memory 4 subc rw, rw subtract direct word gpr from direct gpr with carry 2 subc rw, [rw] subtract indirect word memory from direct gpr with carry 2 subc rw, [rw +] subtract indirect word memory from direct gpr with carry and post-increment source pointer by 2 2 subc rw, #data3 subtract immediate word data from direct gpr with carry 2 subc reg, #data16 subtract immediate word data from direct register with carry 4 subc reg, mem subtract direct word memory from direct register with carry 4 subc mem, reg subtract direct word register from direct memory with carry 4 subcb rb, rb subtract direct byte gpr from direct gpr with carry 2 subcb rb, [rw] subtract indirect byte memory from direct gpr with carry 2 subcb rb, [rw +] subtract indirect byte memory from direct gpr with carry and post-increment source pointer by 1 2 subcb rb, #data3 subtract immediate byte data from direct gpr with carry 2 subcb reg, #data8 subtract immediate byte data from direct register with carry 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 13 version 1.2, 12.97 c166 family instruction set instruction set summary arithmetic operations (contd) subcb reg, mem subtract direct byte memory from direct register with carry 4 subcb mem, reg subtract direct byte register from direct memory with carry 4 mul rw, rw signed multiply direct gpr by direct gpr (16-16-bit) 2 mulu rw, rw unsigned multiply direct gpr by direct gpr (16-16-bit) 2 div rw signed divide register mdl by direct gpr (16-/16-bit) 2 divl rw signed long divide register md by direct gpr (32-/16-bit) 2 divlu rw unsigned long divide register md by direct gpr (32-/16-bit) 2 divu rw unsigned divide register mdl by direct gpr (16-/16-bit) 2 cpl rw complement direct word gpr 2 cplb rb complement direct byte gpr 2 neg rw negate direct word gpr 2 negb rb negate direct byte gpr 2 logical instructions and rw, rw bitwise and direct word gpr with direct gpr 2 and rw, [rw] bitwise and indirect word memory with direct gpr 2 and rw, [rw +] bitwise and indirect word memory with direct gpr and post-increment source pointer by 2 2 and rw, #data3 bitwise and immediate word data with direct gpr 2 and reg, #data16 bitwise and immediate word data with direct register 4 and reg, mem bitwise and direct word memory with direct register 4 and mem, reg bitwise and direct word register with direct memory 4 andb rb, rb bitwise and direct byte gpr with direct gpr 2 andb rb, [rw] bitwise and indirect byte memory with direct gpr 2 andb rb, [rw +] bitwise and indirect byte memory with direct gpr and post-increment source pointer by 1 2 andb rb, #data3 bitwise and immediate byte data with direct gpr 2 andb reg, #data8 bitwise and immediate byte data with direct register 4 andb reg, mem bitwise and direct byte memory with direct register 4 andb mem, reg bitwise and direct byte register with direct memory 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 14 version 1.2, 12.97 c166 family instruction set instruction set summary logical instructions (contd) or rw, rw bitwise or direct word gpr with direct gpr 2 or rw, [rw] bitwise or indirect word memory with direct gpr 2 or rw, [rw +] bitwise or indirect word memory with direct gpr and post-increment source pointer by 2 2 or rw, #data3 bitwise or immediate word data with direct gpr 2 or reg, #data16 bitwise or immediate word data with direct register 4 or reg, mem bitwise or direct word memory with direct register 4 or mem, reg bitwise or direct word register with direct memory 4 orb rb, rb bitwise or direct byte gpr with direct gpr 2 orb rb, [rw] bitwise or indirect byte memory with direct gpr 2 orb rb, [rw +] bitwise or indirect byte memory with direct gpr and post-increment source pointer by 1 2 orb rb, #data3 bitwise or immediate byte data with direct gpr 2 orb reg, #data8 bitwise or immediate byte data with direct register 4 orb reg, mem bitwise or direct byte memory with direct register 4 orb mem, reg bitwise or direct byte register with direct memory 4 xor rw, rw bitwise xor direct word gpr with direct gpr 2 xor rw, [rw] bitwise xor indirect word memory with direct gpr 2 xor rw, [rw +] bitwise xor indirect word memory with direct gpr and post-increment source pointer by 2 2 xor rw, #data3 bitwise xor immediate word data with direct gpr 2 xor reg, #data16 bitwise xor immediate word data with direct register 4 xor reg, mem bitwise xor direct word memory with direct register 4 xor mem, reg bitwise xor direct word register with direct memory 4 xorb rb, rb bitwise xor direct byte gpr with direct gpr 2 xorb rb, [rw] bitwise xor indirect byte memory with direct gpr 2 xorb rb, [rw +] bitwise xor indirect byte memory with direct gpr and post-increment source pointer by 1 2 xorb rb, #data3 bitwise xor immediate byte data with direct gpr 2 xorb reg, #data8 bitwise xor immediate byte data with direct register 4 xorb reg, mem bitwise xor direct byte memory with direct register 4 xorb mem, reg bitwise xor direct byte register with direct memory 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 15 version 1.2, 12.97 c166 family instruction set instruction set summary boolean bit manipulation operations bclr bitaddr clear direct bit 2 bset bitaddr set direct bit 2 bmov bitaddr, bitaddr move direct bit to direct bit 4 bmovn bitaddr, bitaddr move negated direct bit to direct bit 4 band bitaddr, bitaddr and direct bit with direct bit 4 bor bitaddr, bitaddr or direct bit with direct bit 4 bxor bitaddr, bitaddr xor direct bit with direct bit 4 bcmp bitaddr, bitaddr compare direct bit to direct bit 4 bfldh bitoff, #mask8, #data8 bitwise modify masked high byte of bit-addressable direct word memory with immediate data 4 bfldl bitoff, #mask8, #data8 bitwise modify masked low byte of bit-addressable direct word memory with immediate data 4 cmp rw, rw compare direct word gpr to direct gpr 2 cmp rw, [rw] compare indirect word memory to direct gpr 2 cmp rw, [rw +] compare indirect word memory to direct gpr and post-increment source pointer by 2 2 cmp rw, #data3 compare immediate word data to direct gpr 2 cmp reg, #data16 compare immediate word data to direct register 4 cmp reg, mem compare direct word memory to direct register 4 cmpb rb, rb compare direct byte gpr to direct gpr 2 cmpb rb, [rw] compare indirect byte memory to direct gpr 2 cmpb rb, [rw +] compare indirect byte memory to direct gpr and post-increment source pointer by 1 2 cmpb rb, #data3 compare immediate byte data to direct gpr 2 cmpb reg, #data8 compare immediate byte data to direct register 4 cmpb reg, mem compare direct byte memory to direct register 4 compare and loop control instructions cmpd1 rw, #data4 compare immediate word data to direct gpr and decrement gpr by 1 2 cmpd1 rw, #data16 compare immediate word data to direct gpr and decrement gpr by 1 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 16 version 1.2, 12.97 c166 family instruction set instruction set summary compare and loop control instructions (contd) cmpd1 rw, mem compare direct word memory to direct gpr and decrement gpr by 1 4 cmpd2 rw, #data4 compare immediate word data to direct gpr and decrement gpr by 2 2 cmpd2 rw, #data16 compare immediate word data to direct gpr and decrement gpr by 2 4 cmpd2 rw, mem compare direct word memory to direct gpr and decrement gpr by 2 4 cmpi1 rw, #data4 compare immediate word data to direct gpr and increment gpr by 1 2 cmpi1 rw, #data16 compare immediate word data to direct gpr and increment gpr by 1 4 cmpi1 rw, mem compare direct word memory to direct gpr and increment gpr by 1 4 cmpi2 rw, #data4 compare immediate word data to direct gpr and increment gpr by 2 2 cmpi2 rw, #data16 compare immediate word data to direct gpr and increment gpr by 2 4 cmpi2 rw, mem compare direct word memory to direct gpr and increment gpr by 2 4 prioritize instruction prior rw, rw determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shift and rotate instructions shl rw, rw shift left direct word gpr; number of shift cycles specified by direct gpr 2 shl rw, #data4 shift left direct word gpr; number of shift cycles specified by immediate data 2 shr rw, rw shift right direct word gpr; number of shift cycles specified by direct gpr 2 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 17 version 1.2, 12.97 c166 family instruction set instruction set summary shift and rotate instructions (contd) shr rw, #data4 shift right direct word gpr; number of shift cycles specified by immediate data 2 rol rw, rw rotate left direct word gpr; number of shift cycles specified by direct gpr 2 rol rw, #data4 rotate left direct word gpr; number of shift cycles specified by immediate data 2 ror rw, rw rotate right direct word gpr; number of shift cycles specified by direct gpr 2 ror rw, #data4 rotate right direct word gpr; number of shift cycles specified by immediate data 2 ashr rw, rw arithmetic (sign bit) shift right direct word gpr; number of shift cycles specified by direct gpr 2 ashr rw, #data4 arithmetic (sign bit) shift right direct word gpr; number of shift cycles specified by immediate data 2 data movement mov rw, rw move direct word gpr to direct gpr 2 mov rw, #data4 move immediate word data to direct gpr 2 mov reg, #data16 move immediate word data to direct register 4 mov rw, [rw] move indirect word memory to direct gpr 2 mov rw, [rw +] move indirect word memory to direct gpr and post-increment source pointer by 2 2 mov [rw], rw move direct word gpr to indirect memory 2 mov [-rw], rw pre-decrement destination pointer by 2 and move direct word gpr to indirect memory 2 mov [rw], [rw] move indirect word memory to indirect memory 2 mov [rw +], [rw] move indirect word memory to indirect memory and post-increment destination pointer by 2 2 mov [rw], [rw +] move indirect word memory to indirect memory and post-increment source pointer by 2 2 mov rw, [rw + #data16] move indirect word memory by base plus constant to direct gpr 4 mov [rw + #data16], rw move direct word gpr to indirect memory by base plus constant 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 18 version 1.2, 12.97 c166 family instruction set instruction set summary data movement (contd) mov [rw], mem move direct word memory to indirect memory 4 mov mem, [rw] move indirect word memory to direct memory 4 mov reg, mem move direct word memory to direct register 4 mov mem, reg move direct word register to direct memory 4 movb rb, rb move direct byte gpr to direct gpr 2 movb rb, #data4 move immediate byte data to direct gpr 2 movb reg, #data8 move immediate byte data to direct register 4 movb rb, [rw] move indirect byte memory to direct gpr 2 movb rb, [rw +] move indirect byte memory to direct gpr and post-increment source pointer by 1 2 movb [rw], rb move direct byte gpr to indirect memory 2 movb [-rw], rb pre-decrement destination pointer by 1 and move direct byte gpr to indirect memory 2 movb [rw], [rw] move indirect byte memory to indirect memory 2 movb [rw +], [rw] move indirect byte memory to indirect memory and post-increment destination pointer by 1 2 movb [rw], [rw +] move indirect byte memory to indirect memory and post-increment source pointer by 1 2 movb rb, [rw + #data16] move indirect byte memory by base plus constant to direct gpr 4 movb [rw + #data16], rb move direct byte gpr to indirect memory by base plus constant 4 movb [rw], mem move direct byte memory to indirect memory 4 movb mem, [rw] move indirect byte memory to direct memory 4 movb reg, mem move direct byte memory to direct register 4 movb mem, reg move direct byte register to direct memory 4 movbs rw, rb move direct byte gpr with sign extension to direct word gpr 2 movbs reg, mem move direct byte memory with sign extension to direct word register 4 movbs mem, reg move direct byte register with sign extension to direct word memory 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 19 version 1.2, 12.97 c166 family instruction set instruction set summary data movement (contd) movbz rw, rb move direct byte gpr with zero extension to direct word gpr 2 movbz reg, mem move direct byte memory with zero extension to direct word register 4 movbz mem, reg move direct byte register with zero extension to direct word memory 4 jump and call operations jmpa cc, caddr jump absolute if condition is met 4 jmpi cc, [rw] jump indirect if condition is met 2 jmpr cc, rel jump relative if condition is met 2 jmps seg, caddr jump absolute to a code segment 4 jb bitaddr, rel jump relative if direct bit is set 4 jbc bitaddr, rel jump relative and clear bit if direct bit is set 4 jnb bitaddr, rel jump relative if direct bit is not set 4 jnbs bitaddr, rel jump relative and set bit if direct bit is not set 4 calla cc, caddr call absolute subroutine if condition is met 4 calli cc, [rw] call indirect subroutine if condition is met 2 callr rel call relative subroutine 2 calls seg, caddr call absolute subroutine in any code segment 4 pcall reg, caddr push direct word register onto system stack and call absolute subroutine 4 trap #trap7 call interrupt service routine via immediate trap number 2 system stack operations pop reg pop direct word register from system stack 2 push reg push direct word register onto system stack 2 scxt reg, #data16 push direct word register onto system stack und update register with immediate data 4 scxt reg, mem push direct word register onto system stack und update register with direct memory 4 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 20 version 1.2, 12.97 c166 family instruction set instruction set summary *) the extended instructions are not available in the sab 8xc166(w) devices. return operations ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp reg return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 system control srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic #irang2 begin atomic sequence *) 2 extr #irang2 begin extended register sequence *) 2 extp rw, #irang2 begin extended page sequence *) 2 extp #pag10, #irang2 begin extended page sequence *) 4 extpr rw, #irang2 begin extended page and register sequence *) 2 extpr #pag10, #irang2 begin extended page and register sequence *) 4 exts rw, #irang2 begin extended segment sequence *) 2 exts #seg8, #irang2 begin extended segment sequence *) 4 extsr rw, #irang2 begin extended segment and register sequence *) 2 extsr #seg8, #irang2 begin extended segment and register sequence *) 4 miscellaneous nop null operation 2 instruction set summary (contd)* mnemonic description bytes 30mar98@15:00h semiconductor group 21 version 1.2, 12.97 c166 family instruction set instruction opcodes 4 instruction opcodes the following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal opcodes. this helps to identify specific instructions when reading executable code, ie. during the debugging phase. notes for opcode lists 1) these instructions are encoded by means of additional bits in the operand field of the instruction x0 h C x7 h : rw, #data3 or rb, #data3 x8 h C xb h : rw, [rw] or rb, [rw] xc h C xf h : rw, [rw +] or rb, [rw +] for these instructions only the lowest four gprs, r0 to r3, can be used as indirect address pointers. 2) these instructions are encoded by means of additional bits in the operand field of the instruction 00xx.xxxx b : exts or atomic 01xx.xxxx b : extp 10xx.xxxx b : extsr or extr 11xx.xxxx b : extpr the atomic and extended instructions are not available in the sab 8xc166(w) devices. notes on the jmpr instructions the condition code to be tested for the jmpr instructions is specified by the opcode. two mnemonic representation alternatives exist for some of the condition codes. notes on the bclr and bset instructions the position of the bit to be set or to be cleared is specified by the opcode. the operand bitoff.n (n = 0 to 15) refers to a particular bit within a bit-addressable word. notes on the undefined opcodes a hardware trap occurs when one of the undefined opcodes signified by ---- is decoded by the cpu. 30mar98@15:00h semiconductor group 22 version 1.2, 12.97 c166 family instruction set instruction opcodes hex- code num- ber of bytes mnemonic operands hex- code num- ber of bytes mnemonic operands 00 2 add rw, rw 20 2 sub rw, rw 01 2 addb rb, rb 21 2 subb rb, rb 02 4 add reg, mem 22 4 sub reg, mem 03 4 addb reg, mem 23 4 subb reg, mem 04 4 add mem, reg 24 4 sub mem, reg 05 4 addb mem, reg 25 4 subb mem, reg 06 4 add reg, #data16 26 4 sub reg, #data16 07 4 addb reg, #data8 27 4 subb reg, #data8 08 2 add rw, [rw +] or rw, [rw] or rw, #data3 1) 28 2 sub rw, [rw +] or rw, [rw] or rw, #data3 1) 09 2 addb rb, [rw +] or rb, [rw] or rb, #data3 1) 29 2 subb rb, [rw +] or rb, [rw] or rb, #data3 1) 0a 4 bfldl bitoff, #mask8, #data8 2a 4 bcmp bitaddr, bitaddr 0b 2 mul rw, rw 2b 2 prior rw, rw 0c 2 rol rw, rw 2c 2 ror rw, rw 0d 2 jmpr cc_uc, rel 2d 2 jmpr cc_eq, rel or cc_z, rel 0e 2 bclr bitoff.0 2e 2 bclr bitoff.2 0f 2 bset bitoff.0 2f 2 bset bitoff.2 10 2 addc rw, rw 30 2 subc rw, rw 11 2 addcb rb, rb 31 2 subcb rb, rb 12 4 addc reg, mem 32 4 subc reg, mem 13 4 addcb reg, mem 33 4 subcb reg, mem 14 4 addc mem, reg 34 4 subc mem, reg 15 4 addcb mem, reg 35 4 subcb mem, reg 16 4 addc reg, #data16 36 4 subc reg, #data16 17 4 addcb reg, #data8 37 4 subcb reg, #data8 18 2 addc rw, [rw +] or rw, [rw] or rw, #data3 1) 38 2 subc rw, [rw +] or rw, [rw] or rw, #data3 1) 19 2 addcb rb, [rw +] or rb, [rw] or rb, #data3 1) 39 2 subcb rb, [rw +] or rb, [rw] or rb, #data3 1) 1a 4 bfldh bitoff, #mask8, #data8 3a 4 bmovn bitaddr, bitaddr 1b 2 mulu rw, rw 3b - - - 1c 2 rol rw, #data4 3c 2 ror rw, #data4 1d 2 jmpr cc_net, rel 3d 2 jmpr cc_ne, rel or cc_nz, rel 1e 2 bclr bitoff.1 3e 2 bclr bitoff.3 1f 2 bset bitoff.1 3f 2 bset bitoff.3 30mar98@15:00h semiconductor group 23 version 1.2, 12.97 c166 family instruction set instruction opcodes hex- code num- ber of bytes mnemonic operands hex- code num- ber of bytes mnemonic operands 40 2 cmp rw, rw 60 2 and rw, rw 41 2 cmpb rb, rb 61 2 andb rb, rb 42 4 cmp reg, mem 62 4 and reg, mem 43 4 cmpb reg, mem 63 4 andb reg, mem 44 - - - 64 4 and mem, reg 45 - - - 65 4 andb mem, reg 46 4 cmp reg, #data16 66 4 and reg, #data16 47 4 cmpb reg, #data8 67 4 andb reg, #data8 48 2 cmp rw, [rw +] or rw, [rw] or rw, #data3 1) 68 2 and rw, [rw +] or rw, [rw] or rw, #data3 1) 49 2 cmpb rb, [rw +] or rb, [rw] or rb, #data3 1) 69 2 andb rb, [rw +] or rb, [rw] or rb, #data3 1) 4a 4 bmov bitaddr, bitaddr 6a 4 band bitaddr, bitaddr 4b 2 div rw 6b 2 divl rw 4c 2 shl rw, rw 6c 2 shr rw, rw 4d 2 jmpr cc_v, rel 6d 2 jmpr cc_n, rel 4e 2 bclr bitoff.4 6e 2 bclr bitoff.6 4f 2 bset bitoff.4 6f 2 bset bitoff.6 50 2 xor rw, rw 70 2 or rw, rw 51 2 xorb rb, rb 71 2 orb rb, rb 52 4 xor reg, mem 72 4 or reg, mem 53 4 xorb reg, mem 73 4 orb reg, mem 54 4 xor mem, reg 74 4 or mem, reg 55 4 xorb mem, reg 75 4 orb mem, reg 56 4 xor reg, #data16 76 4 or reg, #data16 57 4 xorb reg, #data8 77 4 orb reg, #data8 58 2 xor rw, [rw +] or rw, [rw] or rw, #data3 1) 78 2 or rw, [rw +] or rw, [rw] or rw, #data3 1) 59 2 xorb rb, [rw +] or rb, [rw] or rb, #data3 1) 79 2 orb rb, [rw +] or rb, [rw] or rb, #data3 1) 5a 4 bor bitaddr, bitaddr 7a 4 bxor bitaddr, bitaddr 5b 2 divu rw 7b 2 divlu rw 5c 2 shl rw, #data4 7c 2 shr rw, #data4 5d 2 jmpr cc_nv, rel 7d 2 jmpr cc_nn, rel 5e 2 bclr bitoff.5 7e 2 bclr bitoff.7 5f 2 bset bitoff.5 7f 2 bset bitoff.7 30mar98@15:00h semiconductor group 24 version 1.2, 12.97 c166 family instruction set instruction opcodes hex- code num- ber of bytes mnemonic operands hex- code num- ber of bytes mnemonic operands 80 2 cmpi1 rw, #data4 a0 2 cmpd1 rw, #data4 81 2 neg rw a1 2 negb rb 82 4 cmpi1 rw, mem a2 4 cmpd1 rw, mem 83 - - - a3 - - - 84 4 mov [rw], mem a4 4 movb [rw], mem 85 - - - a5 4 diswdt 86 4 cmpi1 rw, #data16 a6 4 cmpd1 rw, #data16 87 4 idle a7 4 srvwdt 88 2 mov [-rw], rw a8 2 mov rw, [rw] 89 2 movb [-rw], rb a9 2 movb rb, [rw] 8a 4 jb bitaddr, rel aa 4 jbc bitaddr, rel 8b - - - ab 2 calli cc, [rw] 8c - - - ac 2 ashr rw, rw 8d 2 jmpr cc_c, rel or cc_ult, rel ad 2 jmpr cc_sgt, rel 8e 2 bclr bitoff.8 ae 2 bclr bitoff.10 8f 2 bset bitoff.8 af 2 bset bitoff.10 90 2 cmpi2 rw, #data4 b0 2 cmpd2 rw, #data4 91 2 cpl rw b1 2 cplb rb 92 4 cmpi2 rw, mem b2 4 cmpd2 rw, mem 93 - - - b3 - - - 94 4 mov mem, [rw] b4 4 movb mem, [rw] 95 - - - b5 4 einit 96 4 cmpi2 rw, #data16 b6 4 cmpd2 rw, #data16 97 4 pwrdn b7 4 srst 98 2 mov rw, [rw+] b8 2 mov [rw], rw 99 2 movb rb, [rw+] b9 2 movb [rw], rb 9a 4 jnb bitaddr, rel ba 4 jnbs bitaddr, rel 9b 2 trap #trap7 bb 2 callr rel 9c 2 jmpi cc, [rw] bc 2 ashr rw, #data4 9d 2 jmpr cc_nc, rel or cc_uge, rel bd 2 jmpr cc_sle, rel 9e 2 bclr bitoff.9 be 2 bclr bitoff.11 9f 2 bset bitoff.9 bf 2 bset bitoff.11 30mar98@15:00h semiconductor group 25 version 1.2, 12.97 c166 family instruction set instruction opcodes hex- code num- ber of bytes mnemonic operands hex- code num- ber of bytes mnemonic operands c0 2 movbz rw, rb e0 2 mov rw, #data4 c1 - - - e1 2 movb rb, #data4 c2 4 movbz reg, mem e2 4 pcall reg, caddr c3 - - - e3 - - - c4 4 mov [rw+#data16], rw e4 4 movb [rw+#data16], rb c5 4 movbz mem, reg e5 - - - c6 4 scxt reg, #data16 e6 4 mov reg, #data16 c7 - - - e7 4 movb reg, #data8 c8 2 mov [rw], [rw] e8 2 mov [rw], [rw+] c9 2 movb [rw], [rw] e9 2 movb [rw], [rw+] ca 4 calla cc, addr ea 4 jmpa cc, caddr cb 2 ret eb 2 retp reg cc 2 nop ec 2 push reg cd 2 jmpr cc_slt, rel ed 2 jmpr cc_ugt, rel ce 2 bclr bitoff.12 ee 2 bclr bitoff.14 cf 2 bset bitoff.12 ef 2 bset bitoff.14 d0 2 movbs rw, rb f0 2 mov rw, rw d1 2 atomic or extr #irang2 2) f1 2 movb rb, rb d2 4 movbs reg, mem f2 4 mov reg, mem d3 - - - f3 4 movb reg, mem d4 4 mov rw, [rw + #data16] f4 4 movb rb, [rw + #data16] d5 4 movbs mem, reg f5 - - - d6 4 scxt reg, mem f6 4 mov mem, reg d7 4 extp(r), exts(r) #pag10,#irang2 #seg8, #irang2 2) f7 4 movb mem, reg d8 2 mov [rw+], [rw] f8 - - - d9 2 movb [rw+], [rw] f9 - - - da 4 calls seg, caddr fa 4 jmps seg, caddr db 2 rets fb 2 reti dc 2 extp(r), exts(r) rw, #irang2 2) fc 2 pop reg dd 2 jmpr cc_sge, rel fd 2 jmpr cc_ule, rel de 2 bclr bitoff.13 fe 2 bclr bitoff.15 df 2 bset bitoff.13 ff 2 bset bitoff.15 30mar98@15:00h semiconductor group 26 version 1.2, 12.97 c166 family instruction set instruction description 5 instruction description this chapter describes each instruction in detail. the instructions are ordered alphabetically, and the description contains the following elements: ?instruction name? specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference. the mnemonics have been chosen with regard to the particular operation which is performed by the specified instruction. ?syntax? specifies the mnemonic opcode and the required formal operands of the instruction as used in the following subsection 'operation'. there are instructions with either none, one, two or three operands, which must be separated from each other by commas: mnemonic {op1 {,op2 {,op3 } } } the syntax for the actual operands of an instruction depends on the selected addressing mode. all of the addressing modes available are summarized at the end of each single instruction description. in contrast to the syntax for the instructions described in the following, the assembler provides much more flexibility in writing c166 family programs (e.g. by generic instructions and by automatically selecting appropriate addressing modes whenever possible), and thus it eases the use of the instruction set. for more information about this item please refer to the assembler manual. ?operation? this part presents a logical description of the operation performed by an instruction by means of a symbolic formula or a high level language construct. the following symbols are used to represent data movement, arithmetic or logical operators. diadic operations: (opx) operator (opy) ? (opy) is moved into (opx) + (opx) is added to (opy) - (opy) is subtracted from (opx) * (opx) is multiplied by (opy) / (opx) is divided by (opy) (opx) is logically and ed with (opy) (opx) is logically or ed with (opy) ? (opx) is logically exclusively or ed with (opy) ? (opx) is compared against (opy) mod (opx) is divided modulo (opy) monadic operations: operator (opx) ? (opx) is logically complemented 30mar98@15:00h semiconductor group 27 version 1.2, 12.97 c166 family instruction set instruction description missing or existing parentheses signify whether the used operand specifies an immediate constant value, an address or a pointer to an address as follows: opx specifies the immediate constant value of opx (opx) specifies the contents of opx (opx n ) specifies the contents of bit n of opx ((opx)) specifies the contents of the contents of opx (ie. opx is used as pointer to the actual operand) the following operands will also be used in the operational description: cp context pointer register csp code segment pointer register ip instruction pointer md multiply/divide register (32 bits wide, consists of mdh and mdl) mdl, mdh multiply/divide low and high registers (each 16 bit wide ) psw program status word register sp system stack pointer register syscon system configuration register c carry condition flag in the psw register v overflow condition flag in the psw register sgtdis segmentation disable bit in the syscon register count temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation tmp temporary variable for an intermediate result 0, 1, 2,... constant values due to the data format of the specified operation ?data types? this part specifies the particular data type according to the instruction. basically, the following data types are possible: bit, byte, word, doubleword except for those instructions which extend byte data to word data, all instructions have only one particular data type. note that the data types mentioned in this subsection do not consider accesses to indirect address pointers or to the system stack which are always performed with word data. moreover, no data type is specified for system control instructions and for those of the branch instructions which do not access any explicitly addressed data. 30mar98@15:00h semiconductor group 28 version 1.2, 12.97 c166 family instruction set instruction description ?description? this part provides a brief verbal description of the action that is executed by the respective instruction. ?condition code? this notifies that the respective instruction contains a condition code, so it is executed, if the specified condition is true, and is skipped, if it is false. the table below summarizes the 16 possible condition codes that can be used within call and branch instructions. the table shows the mnemonic abbreviations, the test that is executed for a specific condition and the internal representation by a 4-bit number. condition code mnemonic cc test description condition code number c cc_uc 1 = 1 unconditional 0 h cc_z z = 1 zero 2 h cc_nz z = 0 not zero 3 h cc_v v = 1 overflow 4 h cc_nv v = 0 no overflow 5 h cc_n n = 1 negative 6 h cc_nn n = 0 not negative 7 h cc_c c = 1 carry 8 h cc_nc c = 0 no carry 9 h cc_eq z = 1 equal 2 h cc_ne z = 0 not equal 3 h cc_ult c = 1 unsigned less than 8 h cc_ule (z c) = 1 unsigned less than or equal f h cc_uge c = 0 unsigned greater than or equal 9 h cc_ugt (z c) = 0 unsigned greater than e h cc_slt (n ? v) = 1 signed less than c h cc_sle (z (n ? v)) = 1 signed less than or equal b h cc_sge (n ? v) = 0 signed greater than or equal d h cc_sgt (z (n ? v)) = 0 signed greater than a h cc_net (z e) = 0 not equal and not end of table 1 h 30mar98@15:00h semiconductor group 29 version 1.2, 12.97 c166 family instruction set instruction description ?condition flags? this part reflects the state of the n, c, v, z and e flags in the psw register which is the state after execution of the corresponding instruction, except if the psw register itself was specified as the destination operand of that instruction (see note). the resulting state of the flags is represented by symbols as follows: '*' the flag is set due to the following standard rules for the corresponding flag: n = 1 : msb of the result is set n = 0 : msb of the result is not set c = 1 : carry occured during operation c = 0 : no carry occured during operation v = 1 : arithmetic overflow occured during operation v = 0 : no arithmetic overflow occured during operation z = 1 : result equals zero z = 0 : result does not equal zero e = 1 : source operand represents the lowest negative number (either 8000h for word data or 80h for byte data) e = 0 : source operand does not represent the lowest negative number for the specified data type 's' the flag is set due to rules which deviate from the described standard. for more details see instruction pages (below) or the alu status flags description. '-' the flag is not affected by the operation. '0' the flag is cleared by the operation. 'nor' the flag contains the logical noring of the two specified bit operands. 'and' the flag contains the logical anding of the two specified bit operands. 'or' the flag contains the logical oring of the two specified bit operands. 'xor' the flag contains the logical xoring of the two specified bit operands. 'b' the flag contains the original value of the specified bit operand. 'b ' the flag contains the complemented value of the specified bit operand. note: if the psw register was specified as the destination operand of an instruction, the condition flags can not be interpreted as just described, because the psw register is modified depending on the data format of the instruction as follows: for word operations, the psw register is overwritten with the word result. for byte operations, the non-addressed byte is cleared and the addressed byte is overwritten. for bit or bit-field operations on the psw register, only the specified bits are modified. supposed that the condition flags were not selected as destination bits, they stay unchanged. this means that they keep the state after execution of the previous instruction. in any case, if the psw was the destination operand of an instruction, the psw flags do not represent the condition flags of this instruction as usual. 30mar98@15:00h semiconductor group 30 version 1.2, 12.97 c166 family instruction set instruction description ?addressing modes? this part specifies which combinations of different addressing modes are available for the required operands. mostly, the selected addressing mode combination is specified by the opcode of the corresponding instruction. however, there are some arithmetic and logical instructions where the addressing mode combination is not specified by the (identical) opcodes but by particular bits within the operand field. the addressing mode entries are made up of three elements: mnemonic shows an example of what operands the respective instruction will accept. format this part specifies the format of the instructions as it is represented in the assembler listing. the figure below shows the reference between the instruction format representation of the assembler and the corresponding internal organization of such an instruction format (n = nibble = 4 bits). the following symbols are used to describe the instruction formats: 00 h through ff h : instruction opcodes 0, 1 : constant values :.... : each of the 4 characters immediately following a colon represents a single bit :..ii : 2-bit short gpr address (rwi) ss : code segment number (seg). 8-bit for c165/7, 2-bit (:..ss) for sab8xc166 :..## : 2-bit immediate constant (#irang2) :.### : 3-bit immediate constant (#data3) c : 4-bit condition code specification (cc) n : 4-bit short gpr address (rwn or rbn) m : 4-bit short gpr address (rwm or rbm) q : 4-bit position of the source bit within the word specified by qq z : 4-bit position of the destination bit within the word specified by zz # : 4-bit immediate constant (#data4) t:ttt0 : 7-bit trap number (#trap7) qq : 8-bit word address of the source bit (bitoff) rr : 8-bit relative target address word offset (rel) rr : 8-bit word address reg zz : 8-bit word address of the destination bit (bitoff) ## : 8-bit immediate constant (#data8) ## xx : 8-bit immediate constant (represented by #data16, byte xx is not significant) @@ : 8-bit immediate constant (#mask8) mm mm : 16-bit address (mem or caddr; low byte, high byte) ## ## : 16-bit immediate constant (#data16; low byte, high byte) number of bytes specifies the size of an instruction in bytes. all c166 family instructions consist of either 2 or 4 bytes. regarding the instruction size, all instructions can be classified as either single word or double word instructions. 30mar98@15:00h semiconductor group 31 version 1.2, 12.97 c166 family instruction set instruction description figure 5-1: instruction format representation notes on the atomic and extended instructions these instructions (atomic, extr, extp, exts, extpr, extsr) disable standard and pec interrupts and class a traps during a sequence of the following 1...4 instructions. the length of the sequence is determined by an operand (op1 or op2, depending on the instruction). the extended instruction additionally change the addressing mechanism during this sequence (see detailled instruction description). the atomic and extended instructions become active immediately, so no additional nops are required. all instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. any instruction type can be used with the atomic and extended instructions. caution: when a class b trap interupts an atomic or extended sequence, this sequence is terminated, the interrupt lock is removed and the standard condition is restored, before the trap routine is executed! the remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions! caution: be careful, when using the atomic and extended instructions with other system control or branch instructions. caution: be careful, when using nested atomic and extended instructions. there is one counter to control the length of such a sequence, ie. issuing an atomic or extended instruction within a sequence will reload the counter with value of the new instruction. note: the atomic and extended instructions are not available in the sab 8xc166(w) devices. the following pages of this section contain a detailled description of each instruction of the c166 family in alphabetical order. bits in ascending order lsb msb representation in the assembler listing: n2n1 n4n3 n6n5 n8n7 high byte 2nd word low byte 2nd word high byte 1st word low byte 1st word internal organization: n8 n7 n6 n5 n4 n3 n2 n1 30mar98@15:00h semiconductor group 32 version 1.2, 12.97 c166 family instruction set instruction description add integer addition add syntax add op1, op2 operation (op1) ? (op1) + (op2) data types word description performs a 2's complement binary addition of the source operand speci- fied by op2 and the destination operand specified by op1. the sum is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a carry is generated from the most significant bit of the specified data type. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes add rw n , rw m 00 nm 2 add rw n , [rw i ] 08 n:10ii 2 add rw n , [rw i +] 08 n:11ii 2 add rw n , #data3 08 n:0### 2 add reg, #data16 06 rr ## ## 4 add reg, mem 02 rr mm mm 4 add mem, reg 04 rr mm mm 4 condition flags e z v c n *** ** 30mar98@15:00h semiconductor group 33 version 1.2, 12.97 c166 family instruction set instruction description addb integer addition addb syntax addb op1, op2 operation (op1) ? (op1) + (op2) data types byte description performs a 2's complement binary addition of the source operand speci- fied by op2 and the destination operand specified by op1. the sum is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a carry is generated from the most significant bit of the specified data type. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes addb rb n , rb m 01 nm 2 addb rb n , [rw i ] 09 n:10ii 2 addb rb n , [rw i +] 09 n:11ii 2 addb rb n , #data3 09 n:0### 2 addb reg, #data16 07 rr ## xx 4 addb reg, mem 03 rr mm mm 4 addb mem, reg 05 rr mm mm 4 condition flags e z v c n *** ** 30mar98@15:00h semiconductor group 34 version 1.2, 12.97 c166 family instruction set instruction description addc integer addition with carry addc syntax addc op1, op2 operation (op1) ? (op1) + (op2) + (c) data types word description performs a 2's complement binary addition of the source operand speci- fied by op2, the destination operand specified by op1 and the previously generated carry bit. the sum is then stored in op1. this instruction can be used to perform multiple precision arithmetic. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero and previous z flag was set. cleared other- wise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a carry is generated from the most significant bit of the specified data type. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes addc rw n , rw m 10 nm 2 addc rw n , [rw i ] 18 n:10ii 2 addc rw n , [rw i +] 18 n:11ii 2 addc rw n , #data3 18 n:0### 2 addc reg, #data16 16 rr ## ## 4 addc reg, mem 12 rr mm mm 4 addc mem, reg 14 rr mm mm 4 condition flags e z v c n *s* * * 30mar98@15:00h semiconductor group 35 version 1.2, 12.97 c166 family instruction set instruction description addcb integer addition with carry addcb syntax addcb op1, op2 operation (op1) ? (op1) + (op2) + (c) data types byte description performs a 2's complement binary addition of the source operand speci- fied by op2, the destination operand specified by op1 and the previously generated carry bit. the sum is then stored in op1. this instruction can be used to perform multiple precision arithmetic. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero and previous z flag was set.. cleared other- wise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a carry is generated from the most significant bit of the specified data type. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes addcb rb n , rb m 11 nm 2 addcb rb n , [rw i ] 19 n:10ii 2 addcb rb n , [rw i +] 19 n:11ii 2 addcb rb n , #data3 19 n:0### 2 addcb reg, #data16 17 rr ## xx 4 addcb reg, mem 13 rr mm mm 4 addcb mem, reg 15 rr mm mm 4 condition flags e z v c n *s* * * 30mar98@15:00h semiconductor group 36 version 1.2, 12.97 c166 family instruction set instruction description and logical and and syntax and op1, op2 operation (op1) ? (op1) (op2) data types word description performs a bitwise logical and of the source operand specified by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes and rw n , rw m 60 nm 2 and rw n , [rw i ] 68 n:10ii 2 and rw n , [rw i +] 68 n:11ii 2 and rw n , #data3 68 n:0### 2 and reg, #data16 66 rr ## ## 4 and reg, mem 62 rr mm mm 4 and mem, reg 64 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 37 version 1.2, 12.97 c166 family instruction set instruction description andb logical and andb syntax andb op1, op2 operation (op1) ? (op1) (op2) data types byte description performs a bitwise logical and of the source operand specified by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes andb rb n , rb m 61 nm 2 andb rb n , [rw i ] 69 n:10ii 2 andb rb n , [rw i +] 69 n:11ii 2 andb rb n , #data3 69 n:0### 2 andb reg, #data16 67 rr ## xx 4 andb reg, mem 63 rr mm mm 4 andb mem, reg 65 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 38 version 1.2, 12.97 c166 family instruction set instruction description ashr arithmetic shift right ashr syntax ashr op1, op2 operation (count) ? (op2) (v) ? 0 (c) ? 0 do while (count) 1 0 (v) ? (c) (v) (c) ? (op1 0 ) (op1 n ) ? (op1 n+1 ) [n=0...14] (count) ? (count) - 1 end while data types word description arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2. to preserve the sign of the original operand op1, the most significant bits of the result are filled with zeros if the original msb was a 0 or with ones if the original msb was a 1. the overflow flag is used as a rounding flag. the lsb is shifted into the carry. only shift values between 0 and 15 are allowed. when using a gpr as the count control, only the least significant 4 bits are used. e always cleared. z set if result equals zero. cleared otherwise. v set if in any cycle of the shift operation a 1 is shifted out of the carry flag. cleared for a shift count of zero. c the carry flag is set according to the last lsb shifted out of op1. cleared for a shift count of zero. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes ashr rw n , rw m ac nm 2 ashr rw n , #data4 bc #n 2 condition flags e z v c n 0*ss* 30mar98@15:00h semiconductor group 39 version 1.2, 12.97 c166 family instruction set instruction description atomic begin atomic sequence atomic syntax atomic op1 operation (count) ? (op1) [1 op1 4] disable interrupts and class a traps do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 enable interrupts and traps description causes standard and pec interrupts and class a hardware traps to be disabled for a specified number of instructions. the atomic instruction becomes immediately active such that no additional nops are required. depending on the value of op1, the period of validity of the atomic sequence extends over the sequence of the next 1 to 4 instructions being executed after the atomic instruction. all instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. any instruction type can be used with the atomic instruction. note the atomic instruction must be used carefully (see introductory note). the atomic instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes atomic #irang2 d1 :00##-0 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 40 version 1.2, 12.97 c166 family instruction set instruction description band bit logical and band syntax band op1, op2 operation (op1) ? (op1) (op2) data types bit description performs a single bit logical and of the source bit specified by op2 and the destination bit specified by op1. the result is then stored in op1. e always cleared. z contains the logical nor of the two specified bits. v contains the logical or of the two specified bits. c contains the logical and of the two specified bits. n contains the logical xor of the two specified bits. addressing modes mnemonic format bytes band bitaddr z.z , bitaddr q.q 6a qq zz qz 4 condition flags e z v c n 0 nor or and xor 30mar98@15:00h semiconductor group 41 version 1.2, 12.97 c166 family instruction set instruction description bclr bit clear bclr syntax bclr op1 operation (op1) ? 0 data types bit description clears the bit specified by op1. this instruction is primarily used for peripheral and system control. e always cleared. z contains the logical negation of the previous state of the specified bit. v always cleared. c always cleared. n contains the previous state of the specified bit. addressing modes mnemonic format bytes bclr bitaddr q.q qe qq 2 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 42 version 1.2, 12.97 c166 family instruction set instruction description bcmp bit to bit compare bcmp syntax bcmp op1, op2 operation (op1) ? (op2) data types bit description performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2. no result is written by this instruction. only the condition codes are updated. note: the meaning of the condition flags for the bcmp instruction is different from the meaning of the flags for the other compare instructions. e always cleared. z contains the logical nor of the two specified bits. v contains the logical or of the two specified bits. c contains the logical and of the two specified bits. n contains the logical xor of the two specified bits. addressing modes mnemonic format bytes bcmp bitaddr z.z , bitaddr q.q 2a qq zz qz 4 condition flags e z v c n 0 nor or and xor 30mar98@15:00h semiconductor group 43 version 1.2, 12.97 c166 family instruction set instruction description bfldh bit field high byte bfldh syntax bfldh op1, op2, op3 operation (tmp) ? (op1) (high byte (tmp)) ? ((high byte (tmp) ? op2) op3) (op1) ? (tmp) data types word description replaces those bits in the high byte of the destination word operand op1 which are selected by a '1' in the and mask op2 with the bits at the corre- sponding positions in the or mask specified by op3. note: op1 bits which shall remain unchanged must have a '0' in the respective bit of both the and mask op2 and the or mask op3. otherwise a 1 in op3 will set the corresponding op1 bit (see ?operation). e always cleared. z set if the word result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the word result is set. cleared other- wise. addressing modes mnemonic format bytes bfldh bitoff q , #mask 8 , #data8 1a qq ## @@ 4 condition flags e z v c n 0*0 0* 30mar98@15:00h semiconductor group 44 version 1.2, 12.97 c166 family instruction set instruction description bfldl bit field low byte bfldl syntax bfldl op1, op2, op3 operation (tmp) ? (op1) (low byte (tmp)) ? ((low byte (tmp) ? op2) op3) (op1) ? (tmp) data types word description replaces those bits in the low byte of the destination word operand op1 which are selected by a '1' in the and mask op2 with the bits at the corre- sponding positions in the or mask specified by op3. note: op1 bits which shall remain unchanged must have a '0' in the respective bit of both the and mask op2 and the or mask op3. otherwise a 1 in op3 will set the corresponding op1 bit (see ?operation). e always cleared. z set if the word result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the word result is set. cleared other- wise. addressing modes mnemonic format bytes bfldl bitoff q , #mask 8 , #data8 0a qq @@ ## 4 condition flags e z v c n 0*0 0* 30mar98@15:00h semiconductor group 45 version 1.2, 12.97 c166 family instruction set instruction description bmov bit to bit move bmov syntax bmov op1, op2 operation (op1) ? (op2) data types bit description moves a single bit from the source operand specified by op2 into the des- tination operand specified by op1. the source bit is examined and the flags are updated accordingly. e always cleared. z contains the logical negation of the previous state of the source bit. v always cleared. c always cleared. n contains the previous state of the source bit. addressing modes mnemonic format bytes bmov bitaddr z.z , bitaddr q.q 4a qq zz qz 4 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 46 version 1.2, 12.97 c166 family instruction set instruction description bmovn bit to bit move and negate bmovn syntax bmovn op1, op2 operation (op1) ? ? (op2) data types bit description moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1. the source bit is examined and the flags are updated accordingly. e always cleared. z contains the logical negation of the previous state of the source bit. v always cleared. c always cleared. n contains the previous state of the source bit. addressing modes mnemonic format bytes bmovn bitaddr z.z , bitaddr q.q 3a qq zz qz 4 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 47 version 1.2, 12.97 c166 family instruction set instruction description bor bit logical or bor syntax bor op1, op2 operation (op1) ? (op1) (op2) data types bit description performs a single bit logical or of the source bit specified by operand op2 with the destination bit specified by operand op1. the ored result is then stored in op1. e always cleared. z contains the logical nor of the two specified bits. v contains the logical or of the two specified bits. c contains the logical and of the two specified bits. n contains the logical xor of the two specified bits. addressing modes mnemonic format bytes bor bitaddr z.z , bitaddr q.q 5a qq zz qz 4 condition flags e z v c n 0 nor or and xor 30mar98@15:00h semiconductor group 48 version 1.2, 12.97 c166 family instruction set instruction description bset bit set bset syntax bset op1 operation (op1) ? 1 data types bit description sets the bit specified by op1. this instruction is primarily used for periph- eral and system control. e always cleared. z contains the logical negation of the previous state of the specified bit. v always cleared. c always cleared. n contains the previous state of the specified bit. addressing modes mnemonic format bytes bset bitaddr q.q qf qq 2 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 49 version 1.2, 12.97 c166 family instruction set instruction description bxor bit logical xor bxor syntax bxor op1, op2 operation (op1) ? (op1) ? (op2) data types bit description performs a single bit logical exclusive or of the source bit specified by operand op2 with the destination bit specified by operand op1. the xored result is then stored in op1. e always cleared. z contains the logical nor of the two specified bits. v contains the logical or of the two specified bits. c contains the logical and of the two specified bits. n contains the logical xor of the two specified bits. addressing modes mnemonic format bytes bxor bitaddr z.z , bitaddr q.q 7a qq zz qz 4 condition flags e z v c n 0 nor or and xor 30mar98@15:00h semiconductor group 50 version 1.2, 12.97 c166 family instruction set instruction description calla call subroutine absolute calla syntax calla op1, op2 operation if (op1) then (sp) ? (sp) - 2 ((sp)) ? (ip) (ip) ? op2 else next instruction end if description if the condition specified by op1 is met, a branch to the absolute memory location specified by the second operand op2 is taken. the value of the instruction pointer, ip, is placed onto the system stack. because the ip always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. if the condition is not met, no action is taken and the next instruc- tion is executed normally. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes calla cc, caddr ca c0 mm mm 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 51 version 1.2, 12.97 c166 family instruction set instruction description calli call subroutine indirect calli syntax calli op1, op2 operation if (op1) then (sp) ? (sp) - 2 ((sp)) ? (ip) (ip) ? op2 else next instruction end if description if the condition specified by op1 is met, a branch to the location specified indirectly by the second operand op2 is taken. the value of the instruction pointer, ip, is placed onto the system stack. because the ip always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. if the condition is not met, no action is taken and the next instruction is executed normally. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes calli cc, [rw n ] ab cn 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 52 version 1.2, 12.97 c166 family instruction set instruction description callr call subroutine relative callr syntax callr op1 operation (sp) ? (sp) - 2 ((sp)) ? (ip) (ip) ? (ip) + sign_extend (op1) description a branch is taken to the location specified by the instruction pointer, ip, plus the relative displacement, op1. the displacement is a two's comple- ment number which is sign extended and counts the relative distance in words. the value of the instruction pointer (ip) is placed onto the system stack. because the ip always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. the value of the ip used in the target address calculation is the address of the instruction following the callr instruction. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes callr rel bb rr 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 53 version 1.2, 12.97 c166 family instruction set instruction description calls call inter-segment subroutine calls syntax calls op1, op2 operation (sp) ? (sp) - 2 ((sp)) ? (csp) (sp) ? (sp) - 2 ((sp)) ? (ip) (csp) ? op1 (ip) ? op1 description a branch is taken to the absolute location specified by op2 within the seg- ment specified by op1. the value of the instruction pointer (ip) is placed onto the system stack. because the ip always points to the instruction fol- lowing the branch instruction, the value stored on the system stack repre- sents the return address to the calling routine. the previous value of the csp is also placed on the system stack to insure correct return to the call- ing segment. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes calls seg, caddr da ss mm mm 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 54 version 1.2, 12.97 c166 family instruction set instruction description cmp integer compare cmp syntax cmp op1, op2 operation (op1) ? (op2) data types word description the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. the flags are set according to the rules of subtraction. the operands remain unchanged. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmp rw n , rw m 40 nm 2 cmp rw n , [rw i ] 48 n:10ii 2 cmp rw n , [rw i +] 48 n:11ii 2 cmp rw n , #data3 48 n:0### 2 cmp reg, #data16 46 rr ## ## 4 cmp reg, mem 42 rr mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 55 version 1.2, 12.97 c166 family instruction set instruction description cmpb integer compare cmpb syntax cmpb op1, op2 operation (op1) ? (op2) data types byte description the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtraction of op2 from op1. the flags are set according to the rules of subtraction. the operands remain unchanged. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmpb rb n , rb m 41 nm 2 cmpb rb n , [rw i ] 49 n:10ii 2 cmpb rb n , [rw i +] 49 n:11ii 2 cmpb rb n , #data3 49 n:0### 2 cmpb reg, #data16 47 rr ## xx 4 cmpb reg, mem 43 rr mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 56 version 1.2, 12.97 c166 family instruction set instruction description cmpd1 integer compare and decrement by 1 cmpd1 syntax cmpd1 op1, op2 operation (op1) ? (op2) (op1) ? (op1) - 1 data types word description this instruction is used to enhance the performance and flexibility of loops. the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtrac- tion of op2 from op1. operand op1 may specify only gpr registers. once the subtraction has completed, the operand op1 is decremented by one. using the set flags, a branch instruction can then be used in conjunc- tion with this instruction to form common high level language for loops of any range. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmpd1 rw n , #data4 a0 #n 2 cmpd1 rw n , #data16 a6 fn ## ## 4 cmpd1 rw n , mem a2 fn mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 57 version 1.2, 12.97 c166 family instruction set instruction description cmpd2 integer compare and decrement by 2 cmpd2 syntax cmpd2 op1, op2 operation (op1) ? (op2) (op1) ? (op1) - 2 data types word description this instruction is used to enhance the performance and flexibility of loops. the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtrac- tion of op2 from op1. operand op1 may specify only gpr registers. once the subtraction has completed, the operand op1 is decremented by two. using the set flags, a branch instruction can then be used in conjunc- tion with this instruction to form common high level language for loops of any range. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmpd2 rw n , #data4 b0 #n 2 cmpd2 rw n , #data16 b6 fn ## ## 4 cmpd2 rw n , mem b2 fn mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 58 version 1.2, 12.97 c166 family instruction set instruction description cmpi1 integer compare and increment by 1 cmpi1 syntax cmpi1 op1, op2 operation (op1) ? (op2) (op1) ? (op1) + 1 data types word description this instruction is used to enhance the performance and flexibility of loops. the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtrac- tion of op2 from op1. operand op1 may specify only gpr registers. once the subtraction has completed, the operand op1 is incremented by one. using the set flags, a branch instruction can then be used in conjunc- tion with this instruction to form common high level language for loops of any range. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmpi1 rw n , #data4 80 #n 2 cmpi1 rw n , #data16 86 fn ## ## 4 cmpi1 rw n , mem 82 fn mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 59 version 1.2, 12.97 c166 family instruction set instruction description cmpi2 integer compare and increment by 2 cmpi2 syntax cmpi2 op1, op2 operation (op1) ? (op2) (op1) ? (op1) + 2 data types word description this instruction is used to enhance the performance and flexibility of loops. the source operand specified by op1 is compared to the source operand specified by op2 by performing a 2's complement binary subtrac- tion of op2 from op1. operand op1 may specify only gpr registers. once the subtraction has completed, the operand op1 is incremented by two. using the set flags, a branch instruction can then be used in conjunc- tion with this instruction to form common high level language for loops of any range. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cmpi2 rw n , #data4 90 #n 2 cmpi2 rw n , #data16 96 fn ## ## 4 cmpi2 rw n , mem 92 fn mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 60 version 1.2, 12.97 c166 family instruction set instruction description cpl integer ones complement cpl syntax cpl op1 operation (op1) ? ? (op1) data types word description performs a 1's complement of the source operand specified by op1. the result is stored back into op1. e set if the value of op1 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cpl rw n 91 n0 2 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 61 version 1.2, 12.97 c166 family instruction set instruction description cplb integer ones complement cplb syntax cpl op1 operation (op1) ? ? (op1) data types byte description performs a 1's complement of the source operand specified by op1. the result is stored back into op1. e set if the value of op1 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes cplb rb n b1 n0 2 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 62 version 1.2, 12.97 c166 family instruction set instruction description diswdt disable watchdog timer diswdt syntax diswdt operation disable the watchdog timer description this instruction disables the watchdog timer. the watchdog timer is ena- bled by a reset. the diswdt instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function. fol- lowing a reset, this instruction can be executed at any time until either a service watchdog timer instruction (srvwdt) or an end of initialization instruction (einit) are executed. once one of these instructions has been executed, the diswdt instruction will have no effect. to insure that this instruction is not accidentally executed, it is implemented as a protected instruction. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes diswdt a5 5a a5 a5 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 63 version 1.2, 12.97 c166 family instruction set instruction description div 16-by-16 signed division div syntax div op1 operation (mdl) ? (mdl) / (op1) (mdh) ? (mdl) mod (op1) data types word description performs a signed 16-bit by 16-bit division of the low order word stored in the md register by the source word operand op1. the signed quotient is then stored in the low order word of the md register (mdl) and the remainder is stored in the high order word of the md register ( mdh). e always cleared. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in a word data type, or if the divisor (op1) was zero. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes div rw n 4b nn 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 64 version 1.2, 12.97 c166 family instruction set instruction description divl 32-by-16 signed division divl syntax divl op1 operation (mdl) ? (md) / (op1) (mdh) ? (md) mod (op1) data types word, doubleword description performs an extended signed 32-bit by 16-bit division of the two words stored in the md register by the source word operand op1. the signed quotient is then stored in the low order word of the md register (mdl) and the remainder is stored in the high order word of the md register ( mdh). e always cleared. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in a word data type, or if the divisor (op1) was zero. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes divl rw n 6b nn 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 65 version 1.2, 12.97 c166 family instruction set instruction description divlu 32-by-16 unsigned division divlu syntax divlu op1 operation (mdl) ? (md) / (op1) (mdh) ? (md) mod (op1) data types word, doubleword description performs an extended unsigned 32-bit by 16-bit division of the two words stored in the md register by the source word operand op1. the unsigned quotient is then stored in the low order word of the md register (mdl) and the remainder is stored in the high order word of the md register ( mdh). e always cleared. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in a word data type, or if the divisor (op1) was zero. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes divlu rw n 7b nn 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 66 version 1.2, 12.97 c166 family instruction set instruction description divu 16-by-16 unsigned division divu syntax divu op1 operation (mdl) ? (mdl) / (op1) (mdh) ? (mdl) mod (op1) data types word description performs an unsigned 16-bit by 16-bit division of the low order word stored in the md register by the source word operand op1. the signed quotient is then stored in the low order word of the md register (mdl) and the remainder is stored in the high order word of the md register ( mdh). e always cleared. z set if result equals zero. cleared otherwise. v set if an arithmetic overflow occurred, ie. the result cannot be repre- sented in a word data type, or if the divisor (op1) was zero. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes divu rw n 5b nn 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 67 version 1.2, 12.97 c166 family instruction set instruction description einit end of initialization einit syntax einit operation end of initialization description this instruction is used to signal the end of the initialization portion of a program. after a reset, the reset output pin rstout is pulled low. it remains low until the einit instruction has been executed at which time it goes high. this enables the program to signal the external circuitry that it has successfully initialized the microcontroller. after the einit instruction has been executed, execution of the disable watchdog timer instruction (diswdt) has no effect. to insure that this instruction is not accidentally executed, it is implemented as a protected instruction. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes einit b5 4a b5 b5 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 68 version 1.2, 12.97 c166 family instruction set instruction description extr begin extended register sequence extr syntax extr op1 operation (count) ? (op1) [1 op1 4] disable interrupts and class a traps sfr_range = extended do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 sfr_range = standard enable interrupts and traps description causes all sfr or sfr bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the extended sfr space for a specified number of instructions. during their execution, both standard and pec interrupts and class a hardware traps are locked. the value of op1 defines the length of the effected instruction sequence. note the extr instruction must be used carefully (see introductory note). the extr instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes extr #irang2 d1 :10##-0 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 69 version 1.2, 12.97 c166 family instruction set instruction description extp begin extended page sequence extp syntax extp op1, op2 operation (count) ? (op2) [1 op2 4] disable interrupts and class a traps data_page = (op1) do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 data_page = (dppx) enable interrupts and traps description overrides the standard dpp addressing scheme of the long and indirect addressing modes for a specified number of instructions. during their exe- cution, both standard and pec interrupts and class a hardware traps are locked. the extp instruction becomes immediately active such that no additional nops are required. for any long ('mem') or indirect ([...]) address in the extp instruction sequence, the 10-bit page number (address bits a23-a14) is not deter- mined by the contents of a dpp register but by the value of op1 itself. the 14-bit page offset (address bits a13-a0) is derived from the long or indi- rect address as usual. the value of op2 defines the length of the effected instruction sequence. note the extp instruction must be used carefully (see introductory note). the extp instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes extp rwm, #irang2 dc :01##-m 2 extp #pag, #irang2 d7 :01##-0 pp 0:00pp 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 70 version 1.2, 12.97 c166 family instruction set instruction description extpr begin extended page and register sequence extpr syntax extpr op1, op2 operation (count) ? (op2) [1 op2 4] disable interrupts and class a traps data_page = (op1) and sfr_range = extended do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 data_page = (dppx) and sfr_range = standard enable interrupts and traps description overrides the standard dpp addressing scheme of the long and indirect addressing modes and causes all sfr or sfr bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the extended sfr space for a specified number of instructions. during their execution, both standard and pec interrupts and class a hardware traps are locked. for any long ('mem') or indirect ([...]) address in the extp instruction sequence, the 10-bit page number (address bits a23-a14) is not deter- mined by the contents of a dpp register but by the value of op1 itself. the 14-bit page offset (address bits a13-a0) is derived from the long or indi- rect address as usual. the value of op2 defines the length of the effected instruction sequence. note the extpr instruction must be used carefully (see introductory note). the extpr instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes extpr rwm, #irang2 dc :11##-m 2 extpr #pag, #irang2 d7 :11##-0 pp 0:00pp 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 71 version 1.2, 12.97 c166 family instruction set instruction description exts begin extended segment sequence exts syntax exts op1, op2 operation (count) ? (op2) [1 op2 4] disable interrupts and class a traps data_segment = (op1) do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 data_page = (dppx) enable interrupts and traps description overrides the standard dpp addressing scheme of the long and indirect addressing modes for a specified number of instructions. during their exe- cution, both standard and pec interrupts and class a hardware traps are locked. the exts instruction becomes immediately active such that no additional nops are required. for any long ('mem') or indirect ([...]) address in an exts instruction sequence, the value of op1 determines the 8-bit segment (address bits a23-a16) valid for the corresponding data access. the long or indirect address itself represents the 16-bit segment offset (address bits a15-a0). the value of op2 defines the length of the effected instruction sequence. note the exts instruction must be used carefully (see introductory note). the exts instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes exts rwm, #irang2 dc :00##-m 2 exts #seg, #irang2 d7 :00##-0 ss 00 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 72 version 1.2, 12.97 c166 family instruction set instruction description extsr begin extended segment and register sequence extsr syntax extsr op1, op2 operation (count) ? (op2) [1 op2 4] disable interrupts and class a traps data_segment = (op1) and sfr_range = extended do while ((count) 1 0 and class_b_trap_condition 1 true) next instruction (count) ? (count) - 1 end while (count) = 0 data_page = (dppx) and sfr_range = standard enable interrupts and traps description overrides the standard dpp addressing scheme of the long and indirect addressing modes and causes all sfr or sfr bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the extended sfr space for a specified number of instructions. during their execution, both standard and pec interrupts and class a hardware traps are locked. the extsr instruction becomes immediately active such that no additional nops are required. for any long ('mem') or indirect ([...]) address in an extsr instruction sequence, the value of op1 determines the 8-bit segment (address bits a23-a16) valid for the corresponding data access. the long or indirect address itself represents the 16-bit segment offset (address bits a15-a0). the value of op2 defines the length of the effected instruction sequence. note the extsr instruction must be used carefully (see introductory note). the extsr instruction is not available in the sab 8xc166(w) devices. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes extsr rwm, #irang2 dc :10##-m 2 extsr #seg, #irang2 d7 :10##-0 ss 00 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 73 version 1.2, 12.97 c166 family instruction set instruction description idle enter idle mode idle syntax idle operation enter idle mode description this instruction causes the part to enter the idle mode. in this mode, the cpu is powered down while the peripherals remain running. it remains powered down until a peripheral interrupt or external interrupt occurs. to insure that this instruction is not accidentally executed, it is implemented as a protected instruction. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes idle 87 78 87 87 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 74 version 1.2, 12.97 c166 family instruction set instruction description jb relative jump if bit set jb syntax jb op1, op2 operation if (op1) = 1 then (ip) ? (ip) + sign_extend (op2) else next instruction end if data types bit description if the bit specified by op1 is set, program execution continues at the loca- tion of the instruction pointer, ip, plus the specified displacement, op2. the displacement is a two's complement number which is sign extended and counts the relative distance in words. the value of the ip used in the target address calculation is the address of the instruction following the jb instruction. if the specified bit is clear, the instruction following the jb instruction is executed. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jb bitaddr q.q , rel 8a qq rr q0 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 75 version 1.2, 12.97 c166 family instruction set instruction description jbc relative jump if bit set and clear bit jbc syntax jbc op1, op2 operation if (op1) = 1 then (op1) = 0 (ip) ? (ip) + sign_extend (op2) else next instruction end if data types bit description if the bit specified by op1 is set, program execution continues at the loca- tion of the instruction pointer, ip, plus the specified displacement, op2. the bit specified by op1 is cleared, allowing implementation of semaphore operations. the displacement is a two's complement number which is sign extended and counts the relative distance in words. the value of the ip used in the target address calculation is the address of the instruction fol- lowing the jbc instruction. if the specified bit was clear, the instruction fol- lowing the jbc instruction is executed. e always cleared. z contains logical negation of the previous state of the specified bit. v always cleared. c always cleared. n contains the previous state of the specified bit. addressing modes mnemonic format bytes jbc bitaddr q.q , rel aa qq rr q0 4 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 76 version 1.2, 12.97 c166 family instruction set instruction description jmpa absolute conditional jump jmpa syntax jmpa op1, op2 operation if (op1) = 1 then (ip) ? op2 else next instruction end if description if the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. if the condition is not met, no action is taken, and the instruction following the jmpa instruction is executed normally. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jmpa cc, caddr ea c0 mm mm 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 77 version 1.2, 12.97 c166 family instruction set instruction description jmpi indirect conditional jump jmpi syntax jmpi op1, op2 operation if (op1) = 1 then (ip) ? op2 else next instruction end if description if the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. if the condition is not met, no action is taken, and the instruction following the jmpi instruction is executed normally. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jmpi cc, [rw n ]9c cn 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 78 version 1.2, 12.97 c166 family instruction set instruction description jmpr relative conditional jump jmpr syntax jmpr op1, op2 operation if (op1) = 1 then (ip) ? (ip) + sign_extend (op2) else next instruction end if description if the condition specified by op1 is met, program execution continues at the location of the instruction pointer, ip, plus the specified displacement, op2. the displacement is a two's complement number which is sign extended and counts the relative distance in words. the value of the ip used in the target address calculation is the address of the instruction fol- lowing the jmpr instruction. if the specified condition is not met, program execution continues normally with the instruction following the jmpr instruction. condition codes see condition code table. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jmpr cc, rel cd rr 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 79 version 1.2, 12.97 c166 family instruction set instruction description jmps absolute inter-segment jump jmps syntax jmps op1, op2 operation (csp) ? op1 (ip) ? op2 description branches unconditionally to the absolute address specified by op2 within the segment specified by op1. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jmps seg, caddr fa ss mm mm 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 80 version 1.2, 12.97 c166 family instruction set instruction description jnb relative jump if bit clear jnb syntax jnb op1, op2 operation if (op1) = 0 then (ip) ? (ip) + sign_extend (op2) else next instruction end if data types bit description if the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, ip, plus the specified displacement, op2. the displacement is a two's complement number which is sign extended and counts the relative distance in words. the value of the ip used in the target address calculation is the address of the instruction following the jnb instruction. if the specified bit is set, the instruction following the jnb instruction is executed. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes jnb bitaddr q.q , rel 9a qq rr q0 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 81 version 1.2, 12.97 c166 family instruction set instruction description jnbs relative jump if bit clear and set bit jnbs syntax jnbs op1, op2 operation if (op1) = 0 then (op1) = 1 (ip) ? (ip) + sign_extend (op2) else next instruction end if data types bit description if the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, ip, plus the specified displacement, op2. the bit specified by op1 is set, allowing implementation of semaphore operations. the displacement is a two's complement number which is sign extended and counts the relative distance in words. the value of the ip used in the target address calculation is the address of the instruction fol- lowing the jnbs instruction. if the specified bit was set, the instruction fol- lowing the jnbs instruction is executed. e always cleared. z contains logical negation of the previous state of the specified bit. v always cleared. c always cleared. n contains the previous state of the specified bit. addressing modes mnemonic format bytes jnbs bitaddr q.q , rel ba qq rr q0 4 condition flags e z v c n 0b 00b 30mar98@15:00h semiconductor group 82 version 1.2, 12.97 c166 family instruction set instruction description mov move data mov syntax mov op1, op2 operation (op1) ? (op2) data types word description moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. the contents of the moved data is examined, and the condition codes are updated accordingly. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if the value of the source operand op2 equals zero. cleared other- wise. v not affected. c not affected. n set if the most significant bit of the source operand op2 is set. cleared otherwise. addressing modes mnemonic format bytes mov rw n , rw m f0 nm 2 mov rw n , #data4 e0 #n 2 mov reg, #data16 e6 rr ## ## 4 mov rw n , [rw m ] a8 nm 2 mov rw n , [rw m +] 98 nm 2 mov [rw m ], rw n b8 nm 2 mov [-rw m ], rw n 88 nm 2 mov [rw n ], [rw m ]c8 nm 2 mov [rw n +], [rw m ]d8 nm 2 mov [rw n ], [rw m +] e8 nm 2 mov rw n , [rw m +#data16] d4 nm ## ## 4 mov [rw m +#data16], rw n c4 nm ## ## 4 mov [rw n ], mem 84 0n mm mm 4 mov mem, [rw n ] 94 0n mm mm 4 mov reg, mem f2 rr mm mm 4 mov mem, reg f6 rr mm mm 4 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 83 version 1.2, 12.97 c166 family instruction set instruction description movb move data movb syntax movb op1, op2 operation (op1) ? (op2) data types byte description moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. the contents of the moved data is examined, and the condition codes are updated accordingly. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if the value of the source operand op2 equals zero. cleared other- wise. v not affected. c not affected. n set if the most significant bit of the source operand op2 is set. cleared otherwise. addressing modes mnemonic format bytes movb rb n , rb m f1 nm 2 movb rb n , #data4 e1 #n 2 movb reg, #data8 e7 rr ## xx 4 movb rb n , [rw m ] a9 nm 2 movb rb n , [rw m +] 99 nm 2 movb [rw m ], rb n b9 nm 2 movb [-rw m ], rb n 89 nm 2 movb [rw n ], [rw m ]c9 nm 2 movb [rw n +], [rw m ]d9 nm 2 movb [rw n ], [rw m +] e9 nm 2 movb rb n , [rw m +#data16] f4 nm ## ## 4 movb [rw m +#data16], rb n e4 nm ## ## 4 movb [rw n ], mem a4 0n mm mm 4 movb mem, [rw n ] b4 0n mm mm 4 movb reg, mem f3 rr mm mm 4 movb mem, reg f7 rr mm mm 4 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 84 version 1.2, 12.97 c166 family instruction set instruction description movbs move byte sign extend movbs syntax movbs op1, op2 operation (low byte op1) ? (op2) if (op2 7 ) = 1 then (high byte op1) ? ff h else (high byte op1) ? 00 h end if data types word, byte description moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. the con- tents of the moved data is examined, and the condition codes are updated accordingly. e always cleared. z set if the value of the source operand op2 equals zero. cleared other- wise. v not affected. c not affected. n set if the most significant bit of the source operand op2 is set. cleared otherwise. addressing modes mnemonic format bytes movbs rw n , rb m d0 mn 2 movbs reg, mem d2 rr mm mm 4 movbs mem, reg d5 rr mm mm 4 condition flags e z v c n 0* - - * 30mar98@15:00h semiconductor group 85 version 1.2, 12.97 c166 family instruction set instruction description movbz move byte zero extend movbz syntax movbz op1, op2 operation (low byte op1) ? (op2) (high byte op1) ? 00 h data types word, byte description moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. the con- tents of the moved data is examined, and the condition codes are updated accordingly. e always cleared. z set if the value of the source operand op2 equals zero. cleared other- wise. v not affected. c not affected. n always cleared. addressing modes mnemonic format bytes movbz rw n , rb m c0 mn 2 movbz reg, mem c2 rr mm mm 4 movbz mem, reg c5 rr mm mm 4 condition flags e z v c n 0* - -0 30mar98@15:00h semiconductor group 86 version 1.2, 12.97 c166 family instruction set instruction description mul signed multiplication mul syntax mul op1, op2 operation (md) ? (op1) * (op2) data types word description performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively. the signed 32-bit result is placed in the md register. e always cleared. z set if the result equals zero. cleared otherwise. v this bit is set if the result cannot be represented in a word data type. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes mul rw n , rw m 0b nm 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 87 version 1.2, 12.97 c166 family instruction set instruction description mulu unsigned multiplication mulu syntax mulu op1, op2 operation (md) ? (op1) * (op2) data types word description performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively. the unsigned 32-bit result is placed in the md register. e always cleared. z set if the result equals zero. cleared otherwise. v this bit is set if the result cannot be represented in a word data type. cleared otherwise. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes mulu rw n , rw m 1b nm 2 condition flags e z v c n 0*s0* 30mar98@15:00h semiconductor group 88 version 1.2, 12.97 c166 family instruction set instruction description neg integer twos complement neg syntax neg op1 operation (op1) ? 0 - (op1) data types word description performs a binary 2's complement of the source operand specified by op1. the result is then stored in op1. e set if the value of op1 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes neg rw n 81 n0 2 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 89 version 1.2, 12.97 c166 family instruction set instruction description negb integer twos complement negb syntax negb op1 operation (op1) ? 0 - (op1) data types byte description performs a binary 2's complement of the source operand specified by op1. the result is then stored in op1. e set if the value of op1 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes negb rb n a1 n0 2 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 90 version 1.2, 12.97 c166 family instruction set instruction description nop no operation nop syntax nop operation no operation description this instruction causes a null operation to be performed. a null operation causes no change in the status of the flags. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes nop cc 00 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 91 version 1.2, 12.97 c166 family instruction set instruction description or logical or or syntax or op1, op2 operation (op1) ? (op1) (op2) data types word description performs a bitwise logical or of the source operand specified by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes or rw n , rw m 70 nm 2 or rw n , [rw i ] 78 n:10ii 2 or rw n , [rw i +] 78 n:11ii 2 or rw n , #data3 78 n:0### 2 or reg, #data16 76 rr ## ## 4 or reg, mem 72 rr mm mm 4 or mem, reg 74 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 92 version 1.2, 12.97 c166 family instruction set instruction description orb logical or orb syntax orb op1, op2 operation (op1) ? (op1) (op2) data types byte description performs a bitwise logical or of the source operand specified by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes orb rb n , rb m 71 nm 2 orb rb n , [rw i ] 79 n:10ii 2 orb rb n , [rw i +] 79 n:11ii 2 orb rb n , #data3 79 n:0### 2 orb reg, #data16 77 rr ## xx 4 orb reg, mem 73 rr mm mm 4 orb mem, reg 75 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 93 version 1.2, 12.97 c166 family instruction set instruction description pcall push word and call subroutine absolute pcall syntax pcall op1, op2 operation (tmp) ? (op1) (sp) ? (sp) - 2 ((sp)) ? (tmp) (sp) ? (sp) - 2 ((sp)) ? (ip) (ip) ? op2 data types word description pushes the word specified by operand op1 and the value of the instruction pointer, ip, onto the system stack, and branches to the absolute memory location specified by the second operand op2. because ip always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. e set if the value of the pushed operand op1 represents the lowest pos- sible negative number. cleared otherwise. used to signal the end of a table. z set if the value of the pushed operand op1 equals zero. cleared other- wise. v not affected. c not affected. n set if the most significant bit of the pushed operand op1 is set. cleared otherwise. addressing modes mnemonic format bytes pcall reg, caddr e2 rr mm mm 4 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 94 version 1.2, 12.97 c166 family instruction set instruction description pop pop word from system stack pop syntax pop op1 operation (tmp) ? ((sp)) (sp) ? (sp) + 2 (op1) ? (tmp) data types word description pops one word from the system stack specified by the stack pointer into the operand specified by op1. the stack pointer is then incremented by two. e set if the value of the popped word represents the lowest possible neg- ative number. cleared otherwise. used to signal the end of a table. z set if the value of the popped word equals zero. cleared otherwise. v not affected. c not affected. n set if the most significant bit of the popped word is set. cleared other- wise. addressing modes mnemonic format bytes pop reg fc rr 2 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 95 version 1.2, 12.97 c166 family instruction set instruction description prior prioritize register prior syntax prior op1, op2 operation (tmp) ? (op2) (count) ? 0 do while (tmp 15 ) 1 1 and (count) 1 15 and (op2) 1 0 (tmp n ) ? (tmp n-1 ) (count) ? (count) + 1 end while (op1) ? (count) data types word description this instruction stores a count value in the word operand specified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its msb is equal to one. if the source operand op2 equals zero, a zero is written to operand op1 and the zero flag is set. otherwise the zero flag is cleared. e always cleared. z set if the source operand op2 equals zero. cleared otherwise. v always cleared. c always cleared. n always cleared. addressing modes mnemonic format bytes prior rw n , rw m 2b nm 2 condition flags e z v c n 0*0 00 30mar98@15:00h semiconductor group 96 version 1.2, 12.97 c166 family instruction set instruction description push push word on system stack push syntax push op1 operation (tmp) ? (op1) (sp) ? (sp) - 2 ((sp)) ? (tmp) data types word description moves the word specified by operand op1 to the location in the internal system stack specified by the stack pointer, after the stack pointer has been decremented by two. e set if the value of the pushed word represents the lowest possible neg- ative number. cleared otherwise. used to signal the end of a table. z set if the value of the pushed word equals zero. cleared otherwise. v not affected. c not affected. n set if the most significant bit of the pushed word is set. cleared other- wise. addressing modes mnemonic format bytes push reg ec rr 2 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 97 version 1.2, 12.97 c166 family instruction set instruction description pwrdn enter power down mode pwrdn syntax pwrdn operation enter power down mode description this instruction causes the part to enter the power down mode. in this mode, all peripherals and the cpu are powered down until the part is externally reset. to insure that this instruction is not accidentally exe- cuted, it is implemented as a protected instruction. to further control the action of this instruction, the pwrdn instruction is only enabled when the non-maskable interrupt pin (nmi ) is in the low state. otherwise, this instruction has no effect. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes pwrdn 97 68 97 97 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 98 version 1.2, 12.97 c166 family instruction set instruction description ret return from subroutine ret syntax ret operation (ip) ? ((sp)) (sp) ? (sp) + 2 description returns from a subroutine. the ip is popped from the system stack. exe- cution resumes at the instruction following the call instruction in the call- ing routine. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes ret cb 00 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 99 version 1.2, 12.97 c166 family instruction set instruction description reti return from interrupt routine reti syntax reti operation (ip) ? ((sp)) (sp) ? (sp) + 2 if (syscon.sgtdis=0) then (csp) ? ((sp)) (sp) ? (sp) + 2 end if (psw) ? ((sp)) (sp) ? (sp) + 2 description returns from an interrupt routine. the psw, ip, and csp are popped off the system stack. execution resumes at the instruction which had been interrupted. the previous system state is restored after the psw has been popped. the csp is only popped if segmentation is enabled. this is indi- cated by the sgtdis bit in the syscon register. e restored from the psw popped from stack. z restored from the psw popped from stack. v restored from the psw popped from stack. c restored from the psw popped from stack. n restored from the psw popped from stack. addressing modes mnemonic format bytes reti fb 88 2 condition flags e z v c n sss ss 30mar98@15:00h semiconductor group 100 version 1.2, 12.97 c166 family instruction set instruction description retp return from subroutine and pop word retp syntax retp op1 operation (ip) ? ((sp)) (sp) ? (sp) + 2 (tmp) ? ((sp)) (sp) ? (sp) + 2 (op1) ? (tmp) data types word description returns from a subroutine. the ip is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op1. execution resumes at the instruction following the call instruction in the calling routine. e set if the value of the word popped into operand op1 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if the value of the word popped into operand op1 equals zero. cleared otherwise. v not affected. c not affected. n set if the most significant bit of the word popped into operand op1 is set. cleared otherwise. addressing modes mnemonic format bytes retp reg eb rr 2 condition flags e z v c n **- -* 30mar98@15:00h semiconductor group 101 version 1.2, 12.97 c166 family instruction set instruction description rets return from inter-segment subroutine rets syntax rets operation (ip) ? ((sp)) (sp) ? (sp) + 2 (csp) ? ((sp)) (sp) ? (sp) + 2 description returns from an inter-segment subroutine. the ip and csp are popped from the system stack. execution resumes at the instruction following the calls instruction in the calling routine. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes rets db 00 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 102 version 1.2, 12.97 c166 family instruction set instruction description rol rotate left rol syntax rol op1, op2 operation (count) ? (op2) (c) ? 0 do while (count) 1 0 (c) ? (op1 15 ) (op1 n ) ? (op1 n-1 ) [n=1...15] (op1 0 ) ? (c) (count) ? (count) - 1 end while data types word description rotates the destination word operand op1 left by as many times as speci- fied by the source operand op2. bit 15 is rotated into bit 0 and into the carry. only shift values between 0 and 15 are allowed. when using a gpr as the count control, only the least significant 4 bits are used. e always cleared. z set if result equals zero. cleared otherwise. v always cleared. c the carry flag is set according to the last msb shifted out of op1. cleared for a rotate count of zero. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes rol rw n , rw m 0c nm 2 rol rw n , #data4 1c #n 2 condition flags e z v c n 0*0s* 30mar98@15:00h semiconductor group 103 version 1.2, 12.97 c166 family instruction set instruction description ror rotate right ror syntax ror op1, op2 operation (count) ? (op2) (c) ? 0 (v) ? 0 do while (count) 1 0 (v) ? (v) (c) (c) ? (op1 0 ) (op1 n ) ? (op1 n+1 ) [n=0...14] (op1 15 ) ? (c) (count) ? (count) - 1 end while data types word description rotates the destination word operand op1 right by as many times as spec- ified by the source operand op2. bit 0 is rotated into bit 15 and into the carry. only shift values between 0 and 15 are allowed. when using a gpr as the count control, only the least significant 4 bits are used. e always cleared. z set if result equals zero. cleared otherwise. v set if in any cycle of the rotate operation a 1 is shifted out of the carry flag. cleared for a rotate count of zero. c the carry flag is set according to the last lsb shifted out of op1. cleared for a rotate count of zero. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes ror rw n , rw m 2c nm 2 ror rw n , #data4 3c #n 2 condition flags e z v c n 0*ss* 30mar98@15:00h semiconductor group 104 version 1.2, 12.97 c166 family instruction set instruction description scxt switch context scxt syntax scxt op1, op2 operation (tmp1) ? (op1) (tmp2) ? (op2) (sp) ? (sp) - 2 ((sp)) ? (tmp1) (op1) ? (tmp2) data types word description used to switch contexts for any register. switching context is a push and load operation. the contents of the register specified by the first operand, op1, are pushed onto the stack. that register is then loaded with the value specified by the second operand, op2. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes scxt reg, #data16 c6 rr ## ## 4 scxt reg, mem d6 rr mm mm 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 105 version 1.2, 12.97 c166 family instruction set instruction description shl shift left shl syntax shl op1, op2 operation (count) ? (op2) (c) ? 0 do while (count) 1 0 (c) ? (op1 15 ) (op1 n ) ? (op1 n-1 ) [n=1...15] (op1 0 ) ? 0 (count) ? (count) - 1 end while data types word description shifts the destination word operand op1 left by as many times as specified by the source operand op2. the least significant bits of the result are filled with zeros accordingly. the msb is shifted into the carry. only shift val- ues between 0 and 15 are allowed. when using a gpr as the count con- trol, only the least significant 4 bits are used. e always cleared. z set if result equals zero. cleared otherwise. v always cleared. c the carry flag is set according to the last msb shifted out of op1. cleared for a shift count of zero. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes shl rw n , rw m 4c nm 2 shl rw n , #data4 5c #n 2 condition flags e z v c n 0*0s* 30mar98@15:00h semiconductor group 106 version 1.2, 12.97 c166 family instruction set instruction description shr shift right shr syntax shr op1, op2 operation (count) ? (op2) (c) ? 0 (v) ? 0 do while (count) 1 0 (v) ? (c) (v) (c) ? (op1 0 ) (op1 n ) ? (op1 n+1 ) [n=0...14] (op1 15 ) ? 0 (count) ? (count) - 1 end while data types word description shifts the destination word operand op1 right by as many times as speci- fied by the source operand op2. the most significant bits of the result are filled with zeros accordingly. since the bits shifted out effectively represent the remainder, the overflow flag is used instead as a rounding flag. this flag together with the carry flag helps the user to determine whether the remainder bits lost were greater than, less than or equal to one half an lsb. only shift values between 0 and 15 are allowed. when using a gpr as the count control, only the least significant 4 bits are used. e always cleared. z set if result equals zero. cleared otherwise. v set if in any cycle of the shift operation a 1 is shifted out of the carry flag. cleared for a shift count of zero. c the carry flag is set according to the last lsb shifted out of op1. cleared for a shift count of zero. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes shr rw n , rw m 6c nm 2 shr rw n , #data4 7c #n 2 condition flags e z v c n 0*ss* 30mar98@15:00h semiconductor group 107 version 1.2, 12.97 c166 family instruction set instruction description srst software reset srst syntax srst operation software reset description this instruction is used to perform a software reset. a software reset has the same effect on the microcontroller as an externally applied hardware reset. to insure that this instruction is not accidentally executed, it is implemented as a protected instruction. e always cleared. z always cleared. v always cleared. c always cleared. n always cleared. addressing modes mnemonic format bytes srst b7 48 b7 b7 4 condition flags e z v c n 000 00 30mar98@15:00h semiconductor group 108 version 1.2, 12.97 c166 family instruction set instruction description srvwdt service watchdog timer srvwdt syntax srvwdt operation service watchdog timer description this instruction services the watchdog timer. it reloads the high order byte of the watchdog timer with a preset value and clears the low byte on every occurrence. once this instruction has been executed, the watchdog timer cannot be disabled. to insure that this instruction is not accidentally executed, it is implemented as a protected instruction. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes srvwdt a7 58 a7 a7 4 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 109 version 1.2, 12.97 c166 family instruction set instruction description sub integer subtraction sub syntax sub op1, op2 operation (op1) ? (op1) - (op2) data types word description performs a 2's complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes sub rw n , rw m 20 nm 2 sub rw n , [rw i ] 28 n:10ii 2 sub rw n , [rw i +] 28 n:11ii 2 sub rw n , #data3 28 n:0### 2 sub reg, #data16 26 rr ## ## 4 sub reg, mem 22 rr mm mm 4 sub mem, reg 24 rr mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 110 version 1.2, 12.97 c166 family instruction set instruction description subb integer subtraction subb syntax subb op1, op2 operation (op1) ? (op1) - (op2) data types byte description performs a 2's complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes subb rb n , rb m 21 nm 2 subb rb n , [rw i ] 29 n:10ii 2 subb rb n , [rw i +] 29 n:11ii 2 subb rb n , #data3 29 n:0### 2 subb reg, #data16 27 rr ## xx 4 subb reg, mem 23 rr mm mm 4 subb mem, reg 25 rr mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 111 version 1.2, 12.97 c166 family instruction set instruction description subc integer subtraction with carry subc syntax subc op1, op2 operation (op1) ? (op1) - (op2) - (c) data types word description performs a 2's complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destina- tion operand specified by op1. the result is then stored in op1. this instruction can be used to perform multiple precision arithmetic. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero and the previous z flag was set. cleared other- wise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes subc rw n , rw m 30 nm 2 subc rw n , [rw i ] 38 n:10ii 2 subc rw n , [rw i +] 38 n:11ii 2 subc rw n , #data3 38 n:0### 2 subc reg, #data16 36 rr ## ## 4 subc reg, mem 32 rr mm mm 4 subc mem, reg 34 rr mm mm 4 condition flags e z v c n *s* s* 30mar98@15:00h semiconductor group 112 version 1.2, 12.97 c166 family instruction set instruction description subcb integer subtraction with carry subcb syntax subcb op1, op2 operation (op1) ? (op1) - (op2) - (c) data types byte description performs a 2's complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destina- tion operand specified by op1. the result is then stored in op1. this instruction can be used to perform multiple precision arithmetic. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v set if an arithmetic underflow occurred, ie. the result cannot be repre- sented in the specified data type. cleared otherwise. c set if a borrow is generated. cleared otherwise. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes subcb rb n , rb m 31 nm 2 subcb rb n , [rw i ] 39 n:10ii 2 subcb rb n , [rw i +] 39 n:11ii 2 subcb rb n , #data3 39 n:0### 2 subcb reg, #data16 37 rr ## xx 4 subcb reg, mem 33 rr mm mm 4 subcb mem, reg 35 rr mm mm 4 condition flags e z v c n ***s* 30mar98@15:00h semiconductor group 113 version 1.2, 12.97 c166 family instruction set instruction description trap software trap trap syntax trap op1 operation (sp) ? (sp) - 2 ((sp)) ? (psw) if (syscon.sgtdis=0) then (sp) ? (sp) - 2 ((sp)) ? (csp) (csp) ? 0 end if (sp) ? (sp) - 2 ((sp)) ? (ip) (ip) ? zero_extend (op1*4) description invokes a trap or interrupt routine based on the specified operand, op1. the invoked routine is determined by branching to the specified vector table entry point. this routine has no indication of whether it was called by software or hardware. system state is preserved identically to hardware interrupt entry except that the cpu priority level is not affected. the reti, return from interrupt, instruction is used to resume execution after the trap or interrupt routine has completed. the csp is pushed if segmentation is enabled. this is indicated by the sgtdis bit in the syscon register. e not affected. z not affected. v not affected. c not affected. n not affected. addressing modes mnemonic format bytes trap #trap7 9b t:ttt0 2 condition flags e z v c n --- -- 30mar98@15:00h semiconductor group 114 version 1.2, 12.97 c166 family instruction set instruction description xor logical exclusive or xor syntax xor op1, op2 operation (op1) ? (op1) ? (op2) data types word description performs a bitwise logical exclusive or of the source operand speci- fied by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes xor rw n , rw m 50 nm 2 xor rw n , [rw i ] 58 n:10ii 2 xor rw n , [rw i +] 58 n:11ii 2 xor rw n , #data3 58 n:0### 2 xor reg, #data16 56 rr ## ## 4 xor reg, mem 52 rr mm mm 4 xor mem, reg 54 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 115 version 1.2, 12.97 c166 family instruction set instruction description xorb logical exclusive or xorb syntax xorb op1, op2 operation (op1) ? (op1) ? (op2) data types byte description performs a bitwise logical exclusive or of the source operand speci- fied by op2 and the destination operand specified by op1. the result is then stored in op1. e set if the value of op2 represents the lowest possible negative number. cleared otherwise. used to signal the end of a table. z set if result equals zero. cleared otherwise. v always cleared. c always cleared. n set if the most significant bit of the result is set. cleared otherwise. addressing modes mnemonic format bytes xorb rb n , rb m 51 nm 2 xorb rb n , [rw i ] 59 n:10ii 2 xorb rb n , [rw i +] 59 n:11ii 2 xorb rb n , #data3 59 n:0### 2 xorb reg, #data16 57 rr ## xx 4 xorb reg, mem 53 rr mm mm 4 xorb mem, reg 55 rr mm mm 4 condition flags e z v c n **00* 30mar98@15:00h semiconductor group 116 version 1.2, 12.97 c166 family instruction set addressing modes 6 addressing modes the siemens 16-bit microcontrollers provide a lot of powerful addressing modes for access to word, byte and bit data (short, long, indirect), or to specify the target address of a branch instruction (absolute, relative, indirect). the different addressing modes use different formats and cover different scopes. short addressing modes all of these addressing modes use an implicit base offset address to specify an 18-bit or 24-bit physical address (sab 80c166 group or c167/5 group, respectively). short addressing modes allow to access the gpr, sfr or bit-addressable memory space: physical address = base address + d * short address note: d is 1 for byte gprs, d is 2 for word gprs. *) the extended special function register (esfr) area is not available in the sab 8xc166(w) devices. mnemonic physical address short address range scope of access rw (cp) + 2*rw rw = 0...15 gprs (word) rb (cp) + 1*rb rb = 0...15 gprs (byte) reg 00fe00 h + 2*reg 00f000 h + 2*reg *) (cp) + 2*(reg 0f h ) (cp) + 1*(reg 0f h ) reg = 00 h ...ef h reg = 00 h ...ef h reg = f0 h ...ff h reg = f0 h ...ff h sfrs (word, low byte) esfrs (word, low byte) *) gprs (word) gprs (bytes) bitoff 00fd00 h + 2*bitoff 00ff00 h + 2*(bitoff ff h ) (cp) + 2*(bitoff 0f h ) bitoff = 00 h ...7f h bitoff = 80 h ...ef h bitoff = f0 h ...ff h ram bit word offset sfr bit word offset gpr bit word offset bitaddr word offset as with bitoff. immediate bit position. bitoff = 00 h ...ff h bitpos = 0...15 any single bit 30mar98@15:00h semiconductor group 117 version 1.2, 12.97 c166 family instruction set addressing modes rw, rb: specifies direct access to any gpr in the currently active context (register bank). both 'rw' and 'rb' require four bits in the instruction format. the base address of the current register bank is determined by the content of register cp. 'rw' specifies a 4-bit word gpr address relative to the base address (cp), while 'rb' specifies a 4 bit byte gpr address relative to the base address (cp). reg: specifies direct access to any (e)sfr or gpr in the currently active context (register bank). 'reg' requires eight bits in the instruction format. short 'reg' addresses from 00 h to ef h always specify (e)sfrs. in that case, the factor ' d ' equates 2 and the base address is 00fe00 h for the standard sfr area or 00f000 h for the extended esfr area. reg accesses to the esfr area require a preceding ext*r instruction to switch the base address (not available in the sab 8xc166(w) devices). depending on the opcode of an instruction, either the total word (for word operations) or the low byte (for byte opera- tions) of an sfr can be addressed via 'reg'. note that the high byte of an sfr cannot be accessed via the 'reg' addressing mode. short 'reg' addresses from f0 h to ff h always specify gprs. in that case, only the lower four bits of 'reg' are significant for physical address generation, and thus it can be regarded as being identical to the address generation described for the 'rb' and 'rw' addressing modes. bitoff: specifies direct access to any word in the bit-addressable memory space. 'bitoff' requires eight bits in the instruction format. depending on the specified 'bitoff' range, dif- ferent base addresses are used to generate physical addresses: short 'bitoff' addresses from 00 h to 7f h use 00fd00 h as a base address, and thus they specify the 128 high- est internal ram word locations (00fd00 h h to 00fdfe h ). short 'bitoff' addresses from 80 h to ef h use 00ff00 h as a base address to specify the highest internal sfr word locations (00ff00 h to 00ffde h ) or use 00f100 h as a base address to specify the highest internal esfr word locations (00f100 h to 00f1de h ). bitoff accesses to the esfr area require a preceding ext*r instruction to switch the base address (not avail- able in the sab 8xc166(w) devices). for short 'bitoff' addresses from f0 h to ff h , only the lowest four bits and the contents of the cp register are used to generate the physi- cal address of the selected word gpr. bitaddr: any bit address is specified by a word address within the bit-addressable memory space (see 'bitoff'), and by a bit position ('bitpos') within that word. thus, 'bitaddr' requires twelve bits in the instruction format. 30mar98@15:00h semiconductor group 118 version 1.2, 12.97 c166 family instruction set addressing modes long addressing mode this addressing mode uses one of the four dpp registers to specify a physical 18-bit or 24-bit address. any word or byte data within the entire address space can be accessed with this mode. the c167/5 devices also support an override mechanism for the dpp adressing scheme. note: word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. after reset, the dpp registers are initialized in a way that all long addresses are directly mapped onto the identical physical addresses. any long 16-bit address consists of two portions, which are interpreted in different ways. bits 13...0 specify a 14-bit data page offset, while bits 15...14 specify the data page pointer (1 of 4), which is to be used to generate the physical 18-bit or 24-bit address (see figure below). figure 6-1: interpretation of a 16-bit long address the sab 8xc166(w) devices support an address space of up to 256 kbyte, while the c167/5 devices support an address space of up to 16 mbyte, so only the lower two or ten bits (respectively) of the selected dpp register content are concatenated with the 14-bit data page offset to build the physical address. the long addressing mode is referred to by the mnemonic mem. mnemonic physical address long address range scope of access mem (dpp0) || mem 3fff h (dpp1) || mem 3fff h (dpp2) || mem 3fff h (dpp3) || mem 3fff h 0000 h ...3fff h 4000 h ...7fff h 8000 h ...bfff h c000 h ...ffff h any word or byte mem pag || mem 3fff h 0000 h ...ffff h (14-bit) any word or byte mem seg || mem 0000 h ...ffff h (16-bit) any word or byte 0 15 14 13 16-bit long address dpp0 dpp1 dpp2 dpp3 14-bit page offset 18/24-bit physical address 30mar98@15:00h semiconductor group 119 version 1.2, 12.97 c166 family instruction set addressing modes dpp override mechansim in the c167/5 other than the older devices from the sab 80c166 group the c167 and c165 devices provide an override mechanism that allows to bypass the dpp addressing scheme temporarily. the extp(r) and exts(r) instructions override this addressing mechanism. instruction extp(r) replaces the content of the respective dpp register, while instruction exts(r) concatenates th complete 16-bit long address with the specified segment base address. the overriding page or segment may be specified directly as a constant (#pag, #seg) or via a word gpr (rw). figure 6-2: overriding the dpp mechanism indirect addressing modes these addressing modes can be regarded as a combination of short and long addressing modes. this means that long 16-bit addresses are specified indirectly by the contents of a word gpr, which is specified directly by a short 4-bit address ('rw'=0 to 15). there are indirect addressing modes, which add a constant value to the gpr contents before the long 16-bit address is calculated. other indirect addressing modes allow decrementing or incrementing the indirect address pointers (gpr content) by 2 or 1 (referring to words or bytes). in each case, one of the four dpp registers is used to specify physical 18-bit or 24-bit addresses. any word or byte data within the entire memory space can be addressed indirectly. note: the exceptions for instructions extp(r) and exts(r), ie. overriding the dpp mechanism, apply in the same way as described for the long addressing modes. some instructions only use the lowest four word gprs (r3...r0) as indirect address pointers, which are specified via short 2-bit addresses in that case. 0 15 14 13 16-bit long address #pag 14-bit page offset 24-bit physical address 0 15 16-bit long address #seg 16-bit segment offset 24-bit physical address extp(r): exts(r): 30mar98@15:00h semiconductor group 120 version 1.2, 12.97 c166 family instruction set addressing modes note: word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. after reset, the dpp registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses. physical addresses are generated from indirect address pointers via the following algorithm: 1) calculate the physical address of the word gpr, which is used as indirect address pointer, using the specified short address ('rw') and the current register bank base address (cp). gpr address = (cp) + 2 * short address 2) pre-decremented indirect address pointers (-rw) are decremented by a data-type- dependent value ( d =1 for byte operations, d =2 for word operations), before the long 16-bit address is generated: (gpr address) = (gpr address) - d ; [optional step!] 3) calculate the long 16-bit address by adding a constant value (if selected) to the content of the indirect address pointer: long address = (gpr pointer) + constant 4) calculate the physical 18-bit or 24-bit address using the resulting long address and the cor- responding dpp register content (see long 'mem' addressing modes). physical address = (dppi) + page offset 5) post-incremented indirect address pointers (rw+) are incremented by a data-type- dependent value ( d =1 for byte operations, d =2 for word operations): (gpr pointer) = (gpr pointer) + d ; [optional step!] the following indirect addressing modes are provided: mnemonic particularities [rw] most instructions accept any gpr (r15...r0) as indirect address pointer. some instructions, however, only accept the lower four gprs (r3...r0). [rw+] the specified indirect address pointer is automatically post-incremented by 2 or 1 (for word or byte data operations) after the access. [-rw] the specified indirect address pointer is automatically pre-decremented by 2 or 1 (for word or byte data operations) before the access. [rw+#data16] the specified 16-bit constant is added to the indirect address pointer, before the long address is calculated. 30mar98@15:00h semiconductor group 121 version 1.2, 12.97 c166 family instruction set addressing modes constants the c166 family instruction set also supports the use of wordwide or bytewide immediate constants. for an optimum utilization of the available code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits. thus, short constants are always zero-extended while long constants are truncated if necessary to match the data format required for the particular operation (see table below): note: immediate constants are always signified by a leading number sign '#'. instruction range (#irang2) the effect of the atomic and extended instructions can be defined for the following 1...4 instructions. this instruction range (1...4) is coded in the 2-bit constant #irang2 and is represented by the values 0...3. branch target addressing modes different addressing modes are provided to specify the target address and segment of jump or call instructions. relative, absolute and indirect modes can be used to update the instruction pointer register (ip), while the code segment pointer register (csp) can only be updated with an absolute value. a special mode is provided to address the interrupt and trap jump vector table, which resides in the lowest portion of code segment 0. mnemonic word operation byte operation #data3 0000 h + data3 00 h + data3 #data4 0000 h + data4 00 h + data4 #data8 0000 h + data8 data8 #data16 data16 data16 ff h #mask 0000 h + mask mask mnemonic target address target segment valid address range caddr (ip) = caddr - caddr = 0000 h ...fffe h rel (ip) = (ip) + 2*rel (ip) = (ip) + 2*(rel +1) - - rel = 00 h ...7f h rel = 80 h ...ff h [rw] (ip) = ((cp) + 2*rw) - rw = 0...15 seg - (csp) = seg seg = 0...255(3) #trap7 (ip) = 0000 h + 4*trap7 (csp) = 0000 h trap7 = 00 h ...7f h 30mar98@15:00h semiconductor group 122 version 1.2, 12.97 c166 family instruction set addressing modes caddr: specifies an absolute 16-bit code address within the current segment. branches may not be taken to odd code addresses. therefore, the least significant bit of 'caddr' must always contain a '0', otherwise a hardware trap would occur. rel: this mnemonic represents an 8-bit signed word offset address relative to the current instruction pointer contents, which points to the instruction after the branch instruction. depending on the offset address range, either forward ('rel'= 00 h to 7f h ) or backward ('rel'= 80 h to ff h ) branches are possible. the branch instruction itself is repeatedly exe- cuted, when 'rel' = '-1' (ff h ) for a word-sized branch instruction, or 'rel' = '-2' (fe h ) for a double-word-sized branch instruction. [rw]: in this case, the 16-bit branch target instruction address is determined indirectly by the content of a word gpr. in contrast to indirect data addresses, indirectly specified code addresses are not calculated via additional pointer registers (eg. dpp registers). branches may not be taken to odd code addresses. therefore, the least significant bit of the address pointer gpr must always contain a '0', otherwise a hardware trap would occur. seg: specifies an absolute code segment number. the devices of the sab 80c166 group support 4 different code segments, while the devices of the c167/5 group support 256 different code segments, so only the two or eight lower bits (respectively) of the 'seg' operand value are used for updating the csp register. #trap7: specifies a particular interrupt or trap number for branching to the corresponding inter- rupt or trap service routine via a jump vector table. trap numbers from 00 h to 7f h can be specified, which allow to access any double word code location within the address range 000000 h ...0001fc h in code segment 0 (ie. the interrupt jump vector table). for the association of trap numbers with the corresponding interrupt or trap sources please refer to chapter interrupt and trap functions. 30mar98@15:00h semiconductor group 123 version 1.2, 12.97 c166 family instruction set instruction state times 7 instruction state times basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. the fastest processing mode is to execute a program fetched from the internal rom. in that case most of the instructions can be processed within just one machine cycle, which is also the general minimum execution time. all external memory accesses are performed by the on-chip external bus controller (ebc), which works in parallel with the cpu. mostly, instructions from external memory cannot be processed as fast as instructions from the internal rom, because some data transfers, which internally can be performed in parallel, have to be performed sequentially via the external interface. in contrast to internal rom program execution, the time required to process an external program additionally depends on the length of the instructions and operands, on the selected bus mode, and on the duration of an external memory cycle, which is partly selectable by the user. processing a program from the internal ram space is not as fast as execution from the internal rom area, but it offers a lot of flexibility (ie. for loading temporary programs into the internal ram via the chip's serial interface, or end-of-line programming via the bootstrap loader). the following description allows evaluating the minimum and maximum program execution times. this will be sufficient for most requirements. for an exact determination of the instructions' state times it is recommended to use the facilities provided by simulators or emulators. this section defines the subsequently used time units, summarizes the minimum (standard) state times of the 16-bit microcontroller instructions, and describes the exceptions from that standard timing. time unit definitions the following time units are used to describe the instructions' processing times: [ f cpu ]: cpu operating frequency (may vary from 1 mhz to 20 mhz). [state]: one state time is specified by one cpu clock period. henceforth, one state is used as the basic time unit, because it represents the shortest period of time which has to be considered for instruction timing evaluations. 1 [state] = 1/ f cpu [s] ; for f cpu = variable = 50 [ns] ; for f cpu = 20 mhz [act]: this ale (address latch enable) cycle time specifies the time required to perform one external memory access. one ale cycle time consists of either two (for demultiplexed exter- nal bus modes) or three (for multiplexed external bus modes) state times plus a number of state times, which is determined by the number of waitstates programmed in the mctc (memory cycle time control) and mttc (memory tristate time control) bit fields of the syscon/busconx reg- isters. in case of demultiplexed external bus modes: 1 * act = (2 + (15 C mctc) + (1 C mttc)) * states = 100 ns ... 900 ns ; for f cpu = 20 mhz in case of multiplexed external bus modes: 1 * act = 3 + (15 C mctc) + (1 C mttc) * states = 150 ns ... 950 ns ; for f cpu = 20 mhz 30mar98@15:00h semiconductor group 124 version 1.2, 12.97 c166 family instruction set instruction state times the total time ( t tot ), which a particular part of a program takes to be processed, can be calculated by the sum of the single instruction processing times ( t in ) of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline, as follows: t tot =t i1 + t i2 + ... + t in + 6 * states the time t in , which a single instruction takes to be processed, consists of a minimum number ( t imin ) plus an additional number ( t iadd ) of instruction state times and/or ale cycle times, as follows: t in =t imin + t iadd minimum state times the table below shows the minimum number of state times required to process an instruction fetched from the internal rom ( t imin (rom)). the minimum number of state times for instructions fetched from the internal ram ( t imin (ram)), or of ale cycle times for instructions fetched from the external memory ( t imin (ext)), can also be easily calculated by means of this table. most of the 16-bit microcontroller instructions - except some of the branches, the multiplication, the division and a special move instruction - require a minimum of two state times. in case of internal rom program execution there is no execution time dependency on the instruction length except for some special branch situations. the injected target instruction of a cache jump instruction can be considered for timing evaluations as if being executed from the internal rom, regardless of which memory area the rest of the current program is really fetched from. for some of the branch instructions the table below represents both the standard number of state times (ie. the corresponding branch is taken) and an additional t imin value in parentheses, which refers to the case that either the branch condition is not met or a cache jump is taken. minimum instruction state times [unit = ns] instruction t imin (rom) [states] t imin (rom) (@ 20 mhz cpu clock) calli, calla calls, callr, pcall jb, jbc, jnb, jnbs jmps jmpa, jmpi, jmpr mul, mulu div, divl, divu, divlu mov[b] rn, [rm+#data16] ret, reti, retp, rets trap all other instructions 4(+2) 4 4(+2) 4 4(+2) 10 20 4 4 4 2 200 (+100) 200 200 (+100) 200 200 (+100) 500 1000 200 200 200 100 30mar98@15:00h semiconductor group 125 version 1.2, 12.97 c166 family instruction set instruction state times instructions executed from the internal ram require the same minimum time as if being fetched from the internal rom plus an instruction-length dependent number of state times, as follows: for 2-byte instructions: t imin (ram) = t imin (rom) + 4 * states for 4-byte instructions: t imin (ram) = t imin (rom) + 6 * states in contrast to the internal rom program execution, the minimum time t imin (ext) to process an external instruction additionally depends on the instruction length. t imin (ext) is either 1 ale cycle time for most of the 2-byte instructions, or 2 ale cycle times for most of the 4-byte instructions. the following formula represents the minimum execution time of instructions fetched from an external memory via a 16-bit wide data bus: for 2-byte instructions: t imin (ext) = 1 * act + ( t imin (rom) - 2) * states for 4-byte instructions: t imin (ext) = 2 * acts + ( t imin (rom) - 2) * states note: for instructions fetched from an external memory via an 8-bit wide data bus, the minimum number of required ale cycle times is twice the number for a 16-bit wide bus. additional state times some operand accesses can extend the execution time of an instruction t in . since the additional time t iadd is mostly caused by internal instruction pipelining, it often will be possible to evade these timing effects in time-critical program modules by means of a suitable rearrangement of the corresponding instruction sequences. simulators and emulators offer a lot of facilities, which support the user in optimizing his program whenever required. ? internal rom operand reads: t iadd = 2 * states both byte and word operand reads always require 2 additional state times. ? internal ram operand reads via indirect addressing modes: t iadd = 0 or 1 * state reading a gpr or any other directly addressed operand within the internal ram space does not cause additional state times. however, reading an indirectly addressed internal ram operand will extend the processing time by 1 state time, if the preceding instruction auto-increments or auto- decrements a gpr as shown in the following example: i n : mov r1 , [r0+] ; auto-increment r0 i n+1 : mov [r3], [r2] ; if r2 points into the internal ram space: ; t iadd = 1 * state in this case, the additional time can simply be avoided by putting another suitable instruction before the instruction i n+1 indirectly reading the internal ram. 30mar98@15:00h semiconductor group 126 version 1.2, 12.97 c166 family instruction set instruction state times ? internal sfr operand reads: t iadd = 0, 1 * state or 2 * states mostly, sfr read accesses do not require additional processing time. in some rare cases, however, either one or two additional state times will be caused by particular sfr operations, as follows: C reading an sfr immediately after an instruction, which writes to the internal sfr space, as shown in the following example: i n : mov t0, #1000h ; write to timer 0 i n+1 : add r3, t1 ; read from timer 1: t iadd = 1 * state C reading the psw register immediately after an instruction, which implicitly updates the condition flags, as shown in the following example: i n : add r0, #1000h ; implicit modification of psw flags i n+1 : band c, z ; read from psw: t iadd = 2 * states C implicitly incrementing or decrementing the sp register immediately after an instruction, which explicitly writes to the sp register, as shown in the following example: i n : mov sp, #0fb00h ; explicit update of the stack pointer i n+1 : scxt r1, #1000h ; implicit decrement of the stack pointer: : t iadd = 2 * states in these cases, the extra state times can be avoided by putting other suitable instructions before the instruction i n+1 reading the sfr. ? external operand reads: t iadd = 1 * act any external operand reading via a 16-bit wide data bus requires one additional ale cycle time. reading word operands via an 8-bit wide data bus takes twice as much time (2 ale cycle times) as the reading of byte operands. ? external operand writes: t iadd = 0 * state ... 1 * act writing an external operand via a 16-bit wide data bus takes one additional ale cycle time. for timing calculations of external program parts, this extra time must always be considered. the value of t iadd which must be considered for timing evaluations of internal program parts, may fluctuate between 0 state times and 1 ale cycle time. this is because external writes are normally performed in parallel to other cpu operations. thus, t iadd could already have been considered in the standard processing time of another instruction. writing a word operand via an 8-bit wide data bus requires twice as much time (2 ale cycle times) as the writing of a byte operand. 30mar98@15:00h semiconductor group 127 version 1.2, 12.97 c166 family instruction set instruction state times ? jumps into the internal rom space: t iadd = 0 or 2 * states the minimum time of 4 state times for standard jumps into the internal rom space will be extended by 2 additional state times, if the branch target instruction is a double word instruction at a non- aligned double word location (xxx2 h , xxx6 h , xxxa h , xxxe h ), as shown in the following example: label : .... ; any non-aligned double word instruction : (eg. at location 0ffe h ) .... : .... i n+1 : jmpa cc _ uc, label ; if a standard branch is taken: : t iadd = 2 * states (t in = 6 * states) a cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, if both the cached jump target instruction and its successor instruction are non-aligned double word instructions, as shown in the following example: label : .... ; any non-aligned double word instruction : (eg. at location 12fa h ) i t+1 : .... ; any non-aligned double word instruction : (eg. at location 12fe h ) i n+1 :jmpr cc _ uc, label ; provided that a cache jump is taken: : t iadd = 2 * states (t in = 4 * states) if required, these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses (xxx0 h , xxx4 h , xxx8 h , xxxc h ). ? testing branch conditions: t iadd = 0 or 1 * states mostly, no extra time is required for conditional branch instructions to decide whether a branch condition is met or not. however, an additional state time is required, if the preceding instruction writes to the psw register, as shown in the following example: i n : bset usr0 ; write to psw i n+1 :jmpr cc _ z, label ; test condition flag in psw: t iadd = 1 * state in this case, the extra state time can simply be intercepted by putting another suitable instruction before the conditional branch instruction. |
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